EP20K100QC240-3 Altera, EP20K100QC240-3 Datasheet - Page 19

• Manufacturer Part Number: EP20K100QC240-3
• Description: IC APEX 20K FPGA 100K 240-PQFP
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K100QC240-3

• Number Of Logic Elements/cells: 4160
• Number Of Labs/clbs: 416
• Total Ram Bits: 53248
• Number Of I /o: 189
• Number Of Gates: 263000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 240-MQFP, 240-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1094

APEX 20K Programmable Logic Device Family Data Sheet
Normal Mode
The normal mode is suitable for general logic applications, combinatorial
functions, or wide decoding functions that can take advantage of a
cascade chain. In normal mode, four data inputs from the LAB local
interconnect and the carry-in are inputs to a four-input LUT. The
Quartus II software Compiler automatically selects the carry-in or the
DATA3 signal as one of the inputs to the LUT. The LUT output can be
combined with the cascade-in signal to form a cascade chain through the
cascade-out signal. LEs in normal mode support packed registers.
Arithmetic Mode
The arithmetic mode is ideal for implementing adders, accumulators, and
comparators. An LE in arithmetic mode uses two 3-input LUTs. One LUT
computes a three-input function; the other generates a carry output. As
shown in
Figure
8, the first LUT uses the carry-in signal and two data
inputs from the LAB local interconnect to generate a combinatorial or
registered output. For example, when implementing an adder, this output
is the sum of three signals: DATA1, DATA2, and carry-in. The second LUT
uses the same three signals to generate a carry-out signal, thereby creating
a carry chain. The arithmetic mode also supports simultaneous use of the
cascade chain. LEs in arithmetic mode can drive out registered and
unregistered versions of the LUT output.
The Quartus II software implements parameterized functions that use the
arithmetic mode automatically where appropriate; the designer does not
need to specify how the carry chain will be used.
Counter Mode
The counter mode offers clock enable, counter enable, synchronous
up/down control, synchronous clear, and synchronous load options. The
counter enable and synchronous up/down control signals are generated
from the data inputs of the LAB local interconnect. The synchronous clear
and synchronous load options are LAB-wide signals that affect all
registers in the LAB. Consequently, if any of the LEs in an LAB use the
counter mode, other LEs in that LAB must be used as part of the same
counter or be used for a combinatorial function. The Quartus II software
automatically places any registers that are not used by the counter into
other LABs.
Altera Corporation
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