EP20K100QC240-3 Altera, EP20K100QC240-3 Datasheet - Page 34

• Manufacturer Part Number: EP20K100QC240-3
• Description: IC APEX 20K FPGA 100K 240-PQFP
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K100QC240-3

• Number Of Logic Elements/cells: 4160
• Number Of Labs/clbs: 416
• Total Ram Bits: 53248
• Number Of I /o: 189
• Number Of Gates: 263000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 240-MQFP, 240-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1094

APEX 20K Programmable Logic Device Family Data Sheet
Figure 22. ESB in Single-Port Mode
Notes to
(1)
(2)
34
All registers can be asynchronously cleared by ESB local interconnect signals, global signals, or the chip-wide reset.
APEX 20KE devices have four dedicated clocks.
Figure
address[ ]
outclock
outclken
inclken
inclock
data[ ]
wren
Dedicated Clocks
22:
(2)
2 or 4
Dedicated Inputs &
Global Signals
4
Content-Addressable Memory
In APEX 20KE devices, the ESB can implement CAM. CAM can be
thought of as the inverse of RAM. When read, RAM outputs the data for
a given address. Conversely, CAM outputs an address for a given data
word. For example, if the data FA12 is stored in address 14, the CAM
outputs 14 when FA12 is driven into it.
CAM is used for high-speed search operations. When searching for data
within a RAM block, the search is performed serially. Thus, finding a
particular data word can take many cycles. CAM searches all addresses in
parallel and outputs the address storing a particular word. When a match
is found, a match flag is set high.
diagram.
Note (1)
D
ENA
D
ENA
Q
Q
D
ENA
Generator
Pulse
Write
Q
Figure 23
Data In
Address
Write Enable
RAM/ROM
shows the CAM block
1,024 × 2
2,048 × 1
Data Out
128 × 16
256 × 8
512 × 4
D
ENA
Altera Corporation
Q
to MegaLAB,
FastTrack &
Local
Interconnect