EP20K100QC240-3 Altera, EP20K100QC240-3 Datasheet - Page 44

• Manufacturer Part Number: EP20K100QC240-3
• Description: IC APEX 20K FPGA 100K 240-PQFP
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K100QC240-3

• Number Of Logic Elements/cells: 4160
• Number Of Labs/clbs: 416
• Total Ram Bits: 53248
• Number Of I /o: 189
• Number Of Gates: 263000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 240-MQFP, 240-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1094

APEX 20K Programmable Logic Device Family Data Sheet
44
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Advanced I/O Standard Support
APEX 20KE IOEs support the following I/O standards: LVTTL,
LVCMOS, 1.8-V I/O, 2.5-V I/O, 3.3-V PCI, PCI-X, 3.3-V AGP, LVDS,
LVPECL, GTL+, CTT, HSTL Class I, SSTL-3 Class I and II, and SSTL-2
Class I and II.
For more information on I/O standards supported by APEX 20KE
devices, see Application Note 117 (Using Selectable I/O Standards in Altera
Devices).
The APEX 20KE device contains eight I/O banks. In QFP packages, the
banks are linked to form four I/O banks. The I/O banks directly support
all standards except LVDS and LVPECL. All I/O banks can support LVDS
and LVPECL with the addition of external resistors. In addition, one block
within a bank contains circuitry to support high-speed True-LVDS and
LVPECL inputs, and another block within a particular bank supports
high-speed True-LVDS and LVPECL outputs. The LVDS blocks support
all of the I/O standards. Each I/O bank has its own VCCIO pins. A single
device can support 1.8-V, 2.5-V, and 3.3-V interfaces; each bank can
support a different standard independently. Each bank can also use a
separate V
standards (such as SSTL-3) independently. Within a bank, any one of the
terminated standards can be supported. EP20K300E and larger
APEX 20KE devices support the LVDS interface for data pins (smaller
devices support LVDS clock pins, but not data pins). All EP20K300E and
larger devices support the LVDS interface for data pins up to 155 Mbit per
channel; EP20K400E devices and larger with an X-suffix on the ordering
code add a serializer/deserializer circuit and PLL for higher-speed
support.
Each bank can support multiple standards with the same VCCIO for
output pins. Each bank can support one voltage-referenced I/O standard,
but it can support multiple I/O standards with the same VCCIO voltage
level. For example, when VCCIO is 3.3 V, a bank can support LVTTL,
LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.
When the LVDS banks are not used as LVDS I/O banks, they support all
of the other I/O standards.
APEX 20KE I/O banks.
REF
level so that each bank can support any of the terminated
Figure 29
shows the arrangement of the
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