EP20K100QC240-3 Altera, EP20K100QC240-3 Datasheet - Page 65

• Manufacturer Part Number: EP20K100QC240-3
• Description: IC APEX 20K FPGA 100K 240-PQFP
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K100QC240-3

• Number Of Logic Elements/cells: 4160
• Number Of Labs/clbs: 416
• Total Ram Bits: 53248
• Number Of I /o: 189
• Number Of Gates: 263000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 240-MQFP, 240-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1094

Altera Corporation
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) The APEX 20KE input buffers are compatible with 1.8-V, 2.5-V and 3.3-V (LVTTL and LVCMOS) signals.
(11) The I
(12) The I
(13) This value is specified for normal device operation. The value may vary during power-up.
(14) Pin pull-up resistance values will be lower if an external source drives the pin higher than V
(15) Capacitance is sample-tested only.
C
C
C
Table 30. APEX 20KE Device Capacitance
Symbol
IN
INCLK
OUT
See the Operating Requirements for Altera Devices Data Sheet.
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 5.75 V for
input currents less than 100 mA and periods shorter than 20 ns.
Numbers in parentheses are for industrial-temperature-range devices.
Maximum V
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to the voltage
shown in the following table based on input duty cycle for input currents less than 100 mA. The overshoot is
dependent upon duty cycle of the signal. The DC case is equivalent to 100% duty cycle.
Vin
4.0V
4.1
4.2
4.3
4.4
4.5
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before V
powered.
Typical values are for T
These values are specified under the APEX 20KE device recommended operating conditions, shown in Table 24 on
page 60.
Refer to Application Note 117 (Using Selectable I/O Standards in Altera Devices) for the V
parameters when VCCIO = 1.8 V.
Additionally, the input buffers are 3.3-V PCI compliant. Input buffers also meet specifications for GTL+, CTT, AGP,
SSTL-2, SSTL-3, and HSTL.
as well as output pins.
Tables 27
OL
OH
Input capacitance
Input capacitance on
dedicated clock pin
Output capacitance
parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins
parameter refers to high-level TTL, PCI, or CMOS output current.
CC
Parameter
100% (DC)
90%
50%
30%
17%
10%
Max. Duty Cycle
through 30:
rise time is 100 ms, and V
A
= 25° C, V
1
Figure 33
compliance on APEX 20K devices.
V
V
V
IN
IN
OUT
CCINT
= 0 V, f = 1.0 MHz
= 0 V, f = 1.0 MHz
For DC Operating Specifications on APEX 20KE I/O standards,
please refer to Application Note 117 (Using Selectable I/O Standards
in Altera Devices).
= 0 V, f = 1.0 MHz
shows the relationship between V
CC
= 1.8 V, and V
must rise monotonically.
Note (15)
APEX 20K Programmable Logic Device Family Data Sheet
Conditions
CCIO
= 1.8 V, 2.5 V or 3.3 V.
CCIO
and V
IH
Min
, V
CCINT
IL
CCINT
, V
CCIO
OH
and V
Max
12
.
, V
8
8
for 3.3-V PCI
OL
CCIO
, and I
are
Unit
pF
pF
pF
I
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