EP20K100QC240-3 Altera, EP20K100QC240-3 Datasheet - Page 18

• Manufacturer Part Number: EP20K100QC240-3
• Description: IC APEX 20K FPGA 100K 240-PQFP
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K100QC240-3

• Number Of Logic Elements/cells: 4160
• Number Of Labs/clbs: 416
• Total Ram Bits: 53248
• Number Of I /o: 189
• Number Of Gates: 263000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 240-MQFP, 240-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1094

APEX 20K Programmable Logic Device Family Data Sheet
Figure 8. APEX 20K LE Operating Modes
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
18
Normal Mode (1)
Arithmetic Mode
Counter Mode
LEs in normal mode support register packing.
There are two LAB-wide clock enables per LAB.
When using the carry-in in normal mode, the packed register feature is unavailable.
A register feedback multiplexer is available on LE1 of each LAB.
The DATA1 and DATA2 input signals can supply counter enable, up or down control, or register feedback signals for
LEs other than the second LE in an LAB.
The LAB-wide synchronous clear and LAB wide synchronous load affect all registers in an LAB.
data1 (5)
data2 (5)
data3 (data)
data1
data2
data3
data4
Figure
(4)
data1
data2
8:
Carry-In
Carry-In (3)
Carry-In
3-Input
3-Input
LUT
LUT
3-Input
3-Input
4-Input
LUT
LUT
LUT
Cascade-In
Cascade-In
Carry-Out
Carry-Out
Cascade-In
Cascade-Out
Cascade-Out
Cascade-Out
LAB-Wide
Synchronous
Load (6)
LAB-Wide
Clock Enable (2)
LAB-Wide
Synchronous
Clear (6)
LAB-Wide
Clock Enable (2)
LAB-Wide
Clock Enable (2)
D
ENA
CLRN
PRN
D
ENA
CLRN
PRN
Q
ENA
D
Q
CLRN
PRN
Q
Altera Corporation
LE-Out
LE-Out
LE-Out
LE-Out
LE-Out
LE-Out