EP20K100QC240-3 Altera, EP20K100QC240-3 Datasheet - Page 72

• Manufacturer Part Number: EP20K100QC240-3
• Description: IC APEX 20K FPGA 100K 240-PQFP
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K100QC240-3

• Number Of Logic Elements/cells: 4160
• Number Of Labs/clbs: 416
• Total Ram Bits: 53248
• Number Of I /o: 189
• Number Of Gates: 263000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 240-MQFP, 240-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1094

APEX 20K Programmable Logic Device Family Data Sheet
72
t
t
t
t
t
t
t
t
t
t
t
SU
H
CO
LUT
ESBRC
ESBWC
ESBWESU
ESBDATASU
ESBDATAH
ESBADDRSU
ESBDATACO1
Table 31. APEX 20K f
Symbol
MAX
LE register setup time before clock
LE register hold time after clock
LE register clock-to-output delay
LUT delay for data-in
ESB Asynchronous read cycle time
ESB Asynchronous write cycle time
ESB WE setup time before clock when using input register
ESB data setup time before clock when using input register
ESB data hold time after clock when using input register
ESB address setup time before clock when using input registers
ESB clock-to-output delay when using output registers
Timing Parameters
Figure 40. Synchronous Bidirectional Pin External Timing
Notes to
(1)
(2)
Table 31
page
The output enable and input registers are LE registers in the LAB adjacent to a
bidirectional row pin. The output enable register is set with “Output Enable
Routing= Signal-Pin” option in the Quartus II software.
The LAB adjacent input register is set with “Decrease Input Delay to Internal Cells=
Off”. This maintains a zero hold time for lab adjacent registers while giving a fast,
position independent setup time. A faster setup time with zero hold time is possible
by setting “Decrease Input Delay to Internal Cells= ON” and moving the input
register farther away from the bidirectional pin. The exact position where zero hold
occurs with the minimum setup time, varies with device density and speed grade.
68.
Dedicated
Clock
Figure
describes the f
40:
(Part 1 of 2)
Output IOE Register
MAX
OE Register
Input Register
D
D
D
CLRN
CLRN
CLRN
timing parameters shown in
PRN
PRN
PRN
Parameter
Q
Q
Q
IOE Register
(1)
(1)
(2)
t
t
XZBIDIR
ZXBIDIR
t
OUTCOBIDIR
t
t
Bidirectional Pin
INSUBIDIR
INHBIDIR
Altera Corporation
Figure 36 on