EP20K100QC240-3 Altera, EP20K100QC240-3 Datasheet - Page 38
![IC APEX 20K FPGA 100K 240-PQFP](/photos/6/72/67260/544-240-pqfp_sml.jpg)
EP20K100QC240-3
Manufacturer Part Number
EP20K100QC240-3
Description
IC APEX 20K FPGA 100K 240-PQFP
Manufacturer
Altera
Series
APEX-20K®r
Datasheet
1.EP20K30ETC144-3.pdf
(117 pages)
Specifications of EP20K100QC240-3
Number Of Logic Elements/cells
4160
Number Of Labs/clbs
416
Total Ram Bits
53248
Number Of I /o
189
Number Of Gates
263000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1094
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP20K100QC240-3N
Manufacturer:
ALTERA
Quantity:
150
Part Number:
EP20K100QC240-3V
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
APEX 20K Programmable Logic Device Family Data Sheet
38
Table 10
options in the Quartus II software.
The Quartus II software compiler can program these delays automatically
to minimize setup time while providing a zero hold time.
how fast bidirectional I/Os are implemented in APEX 20K devices.
The register in the APEX 20K IOE can be programmed to power-up high
or low after configuration is complete. If it is programmed to power-up
low, an asynchronous clear can control the register. If it is programmed to
power-up high, the register cannot be asynchronously cleared or preset.
This feature is useful for cases where the APEX 20K device controls an
active-low input or another device; it prevents inadvertent activation of
the input upon power-up.
Input pin to core delay
Input pin to input register delay
Core to output register delay
Output register t
Table 10. APEX 20K Programmable Delay Chains
Programmable Delays
describes the APEX 20K programmable delays and their logic
CO
delay
Decrease input delay to internal cells
Decrease input delay to input register
Decrease input delay to output register
Increase delay to output pin
Quartus II Logic Option
Altera Corporation
Figure 25
shows