LPC1850FET256,551 NXP Semiconductors, LPC1850FET256,551 Datasheet - Page 70

• Manufacturer Part Number: LPC1850FET256,551
• Description: MCU 32BIT ARM CORTEX M3 256BGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1850FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, QEI, SD/MMC, SPI, SSI, SSP, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 200K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Processor Series: LPC1850
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 200 KB
• Interface Type: SPI Flash (SPIFI), USB, Ethernet, LCD, External Memory Controller, I2C
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 6
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6682

Table 16.
C
Symbol
Common to read and write cycles
t
Read cycle parameters
t
t
t
t
t
t
t
t
t
Write cycle parameters
t
t
t
t
t
t
t
CSLAV
OELAV
CSLOEL
am
h(D)
CSHOEH
OEHANV
OELOEH
BLSLAV
CSHBLSH
CSLWEL
CSLBLSL
WELDV
CSLDV
WELWEH
BLSLBLSH
WEHANV
L
= 30 pF; T
Parameter
CS LOW to address valid
time
OE LOW to address valid
time
CS LOW to OE LOW time
memory access time
data input hold time
CS HIGH to OE HIGH time
OE HIGH to address invalid
time
OE LOW to OE HIGH time
BLS LOW to address valid
time
CS HIGH to BLS HIGH time
CS LOW to WE LOW time
CS LOW to BLS LOW time
WE LOW to data valid time
CS LOW to data valid time
WE LOW to WE HIGH time
BLS LOW to BLS HIGH
time
WE HIGH to address invalid
time
Dynamic characteristics: Static external memory interface
amb
11.7 Static external memory interface
=

40

C to 85
[1][2]
[1][6]

C; V
[1]
DD(REG)(3V3)
Conditions
and V
DD(IO)
[3][4]
[5]
[3]
[3]
[3]
over specified ranges <tbd>; AHB clock = 1 MHz
Min
<tbd>
<tbd>
<tbd> + T
WAITOEN
(WAITRD  WAITOEN + 1) 
T
<tbd>
<tbd>
<tbd>
<tbd> + (WAITRD 
WAITOEN + 1)  T
<tbd>
<tbd>
<tbd> + T
WAITWEN)
0.88
0.68
0
<tbd> + T
(WAITWR  WAITWEN + 1)
<tbd> + T
(WAITWR  WAITWEN + 3)
<tbd> + T
cy(CCLK)
 <tbd>
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)

 (1 +


cy(CCLK)
Typ
<tbd>
<tbd>
0 + T
(WAITRD  WAITOEN + 1) 
T
<tbd>
<tbd>
<tbd>
0 + (WAITRD  WAITOEN +
1)  T
<tbd>
<tbd>
<tbd> + T
WAITWEN)
0.49
2.54
2.64
0 + T
WAITWEN + 1)
0 + T
WAITWEN + 3)
<tbd> + T
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
 <tbd>
cy(CCLK)
cy(CCLK)
 WAITOEN
 (WAITWR 
 (WAITWR 
 (1 +
<tbd>
<tbd>
<tbd> + T
<tbd>
<tbd>
<tbd>
Max
WAITOEN
(WAITRD  WAITOEN + 1) 
T
<tbd>
<tbd> + (WAITRD 
WAITOEN + 1)  T
<tbd>
<tbd> + T
WAITWEN)
0.98
5.86
4.79
<tbd> + T
(WAITWR  WAITWEN + 1)
<tbd> + T
(WAITWR  WAITWEN + 3)
<tbd> + T
cy(CCLK)
 <tbd>
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)

 (1 +


cy(CCLK)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns