LPC1850FET256,551 NXP Semiconductors, LPC1850FET256,551 Datasheet - Page 69
![MCU 32BIT ARM CORTEX M3 256BGA](/photos/27/78/277808/lbga156_sml.jpg)
LPC1850FET256,551
Manufacturer Part Number
LPC1850FET256,551
Description
MCU 32BIT ARM CORTEX M3 256BGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheet
1.LPC1830FET256551.pdf
(87 pages)
Specifications of LPC1850FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, QEI, SD/MMC, SPI, SSI, SSP, UART/USART, USB, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
200K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Processor Series
LPC1850
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
200 KB
Interface Type
SPI Flash (SPIFI), USB, Ethernet, LCD, External Memory Controller, I2C
Maximum Clock Frequency
150 MHz
Number Of Programmable I/os
80
Number Of Timers
6
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6682
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1850FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC1850FET256,551
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
Table 15.
C
LPC1850_30_20_10
Objective data sheet
Symbol
Common
t
t
t
t
t
t
t
t
t
t
t
t
Read cycle parameters
t
t
Write cycle parameters
t
t
d(SV)
h(S)
d(RASV)
h(RAS)
d(CASV)
h(CAS)
d(WV)
h(W)
d(GV)
h(G)
d(AV)
h(A)
su(D)
h(D)
d(QV)
h(Q)
L
= 30 pF; T
Dynamic characteristics: Dynamic external memory interface
amb
Parameter
chip select valid delay time
chip select hold time
row address strobe valid delay time
row address strobe hold time
column address strobe valid delay time
column address strobe hold time
write valid delay time
write hold time
output enable valid delay time
output enable hold time
address valid delay time
address hold time
data input set-up time
data input hold time
data output valid delay time
data output hold time
11.6 Dynamic external memory interface
=
40
C to 85
C; V
DD(REG)(3V3)
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 17 February 2011
and V
DD(IO)
over specified ranges <tbd>; AHB clock = 1 MHz.
Conditions
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
Min
-
<tbd> <tbd>
-
<tbd> <tbd>
-
<tbd> <tbd>
-
<tbd> <tbd>
-
<tbd> <tbd>
-
<tbd> <tbd>
<tbd> <tbd>
<tbd> <tbd>
-
<tbd> <tbd>
Typ
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
© NXP B.V. 2011. All rights reserved.
<tbd>
-
<tbd>
<tbd>
-
<tbd>
-
<tbd>
-
Max
<tbd>
-
<tbd>
-
-
-
-
69 of 87
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns