LPC1850FET256,551 NXP Semiconductors, LPC1850FET256,551 Datasheet - Page 14

• Manufacturer Part Number: LPC1850FET256,551
• Description: MCU 32BIT ARM CORTEX M3 256BGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1850FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, QEI, SD/MMC, SPI, SSI, SSP, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 200K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Processor Series: LPC1850
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 200 KB
• Interface Type: SPI Flash (SPIFI), USB, Ethernet, LCD, External Memory Controller, I2C
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 6
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6682

NXP Semiconductors
Table 3.
LPC1850_30_20_10
Objective data sheet
Symbol
P5_6
P5_7
P6_0
P6_1
P6_2
P6_3
P6_4
P6_5
[2]
[2]
[2]
[2]
[2]
[2]
[2]
Pin description
T13
R12
M12 I; PU
R15
L13
P15
R16
P16
…continued
Reset
state
[1]
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
Type Description
I/O
O
I/O
-
I/O
O
I/O
-
I/O
O
-
-
I/O
O
I/O
I/O
I/O
O
I/O
I/O
I/O
O
-
O
I/O
I
O
O
I/O
O
I
O
All information provided in this document is subject to legal disclaimers.
GPIO2[15] — General purpose digital input/output pin.
MCOB1 — Motor control PWM channel 1, output B.
EXTBUS_D10 — External memory data line 10.
n.c.
GPIO2[7] — General purpose digital input/output pin.
MCOA2 — Motor control PWM channel 2, output A.
EXTBUS_D11 — External memory data line 11.
n.c.
I2S_RX_SCK — Receive Clock. It is driven by the master and received by the
slave. Corresponds to the signal SCK in the I
I2S_RX_MCLK — I2S receive master clock.
n.c.
n.c.
GPIO3[0] — General purpose digital input/output pin.
EXTBUS_DYCS1 — SDRAM chip select 1.
U0_UCLK — Serial clock input/output for USART0 in synchronous mode.
I2S_RX_WS — Receive Word Select. It is driven by the master and received
by the slave. Corresponds to the signal WS in the I
GPIO3[1] — General purpose digital input/output pin.
EXTBUS_CKEOUT1 — SDRAM clock enable 1.
U0_DIR — RS-485/EIA-485 output enable/direction control for USART0.
I2S_RX_SDA — I
the receiver. Corresponds to the signal SD in the I
GPIO3[2] — General purpose digital input/output pin.
USB0_PWR_EN — VBUS drive signal (towards external charge pump or
power management unit); indicates that Vbus must be driven (active high).
n.c.
EXTBUS_CS1 — LOW active Chip Select 1 signal.
GPIO3[3] — General purpose digital input/output pin.
CTIN_6 — SCT input 6. Capture input 1 of timer 3.
U0_TXD — Transmitter output for USART0.
EXTBUS_CAS — LOW active SDRAM Column Address Strobe.
GPIO3[4] — General purpose digital input/output pin.
CTOUT_6 — SCT output 6. Match output 2 of timer 1.
U0_RXD — Receiver input for USART0.
EXTBUS_RAS — LOW active SDRAM Row Address Strobe.
Rev. 1.2 — 17 February 2011
2
S Receive data. It is driven by the transmitter and read by
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
2
S-bus specification.
2
2
S-bus specification.
S-bus specification.
© NXP B.V. 2011. All rights reserved.
14 of 87