LPC1850FET256,551 NXP Semiconductors, LPC1850FET256,551 Datasheet - Page 7

• Manufacturer Part Number: LPC1850FET256,551
• Description: MCU 32BIT ARM CORTEX M3 256BGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1850FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, QEI, SD/MMC, SPI, SSI, SSP, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 200K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Processor Series: LPC1850
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 200 KB
• Interface Type: SPI Flash (SPIFI), USB, Ethernet, LCD, External Memory Controller, I2C
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 6
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6682

NXP Semiconductors
Table 3.
LPC1850_30_20_10
Objective data sheet
Symbol
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
P1_8
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
Pin description
P2
R2
R3
P5
T3
R5
T4
T5
R7
…continued
Reset
state
[1]
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
Type Description
I/O
I
I/O
-
I/O
O
I/O
-
I/O
O
I/O
-
I/O
O
-
O
I/O
O
-
O
I/O
O
-
O
I/O
I
-
O
I/O
I
O
I/O
I/O
O
O
I/O
All information provided in this document is subject to legal disclaimers.
GPIO0[4] — General purpose digital input/output pin.
CTIN_3 — SCT input 3. Capture input 1 of timer 1.
EXTBUS_A5 — External memory address line 5.
n.c.
GPIO0[8] — General purpose digital input/output pin.
CTOUT_7 — SCT output 7. Match output 3 of timer 1.
EXTBUS_A6 — External memory address line 6. Boot control pin 0 (see
Table
n.c.
GPIO0[9] — General purpose digital input/output pin.
CTOUT_6 — SCT output 6. Match output 2 of timer 1.
EXTBUS_A7 — External memory address line 7. Boot control pin 1 (see
Table
n.c.
GPIO0[10] — General purpose digital input/output pin.
CTOUT_8 — SCT output 8. Match output 0 of timer 2.
n.c.
EXTBUS_OE — LOW active Output Enable signal.
GPIO0[11] — General purpose digital input/output pin.
CTOUT_9 — SCT output 9. Match output 1 of timer 2.
n.c.
EXTBUS_BLS0 — LOW active Byte Lane select signal 0.
GPIO1[8] — General purpose digital input/output pin.
CTOUT_10 — SCT output 10. Match output 2 of timer 2.
n.c.
EXTBUS_CS0 — LOW active Chip Select 0 signal.
GPIO1[9] — General purpose digital input/output pin.
CTIN_5 — SCT input 5. Capture input 2 of timer 2.
n.c.
EXTBUS_WE — LOW active Write Enable signal.
GPIO1[0] — General purpose digital input/output pin.
U1_DSR — Data Set Ready input for UART1.
CTOUT_13 — SCT output 13. Match output 1 of timer 3.
EXTBUS_D0 — External memory data line 0.
GPIO1[1] — General purpose digital input/output pin.
U1_DTR — Data Terminal Ready output for UART1.
CTOUT_12 — SCT output 12. Match output 0 of timer 3.
EXTBUS_D1 — External memory data line 1.
Rev. 1.2 — 17 February 2011
5).
5).
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
© NXP B.V. 2011. All rights reserved.
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