LPC1850FET256,551 NXP Semiconductors, LPC1850FET256,551 Datasheet - Page 33

• Manufacturer Part Number: LPC1850FET256,551
• Description: MCU 32BIT ARM CORTEX M3 256BGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1850FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, QEI, SD/MMC, SPI, SSI, SSP, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 200K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Processor Series: LPC1850
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 200 KB
• Interface Type: SPI Flash (SPIFI), USB, Ethernet, LCD, External Memory Controller, I2C
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 6
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6682

NXP Semiconductors
Table 4.
[1]
LPC1850_30_20_10
Objective data sheet
Boot mode BOOT_SRC
Pin state
UART
SPIFI
EMC 8-bit
EMC 16-bit
EMC 32-bit
USB0
USB1
SPI (SSP)
The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
Boot mode when OTP BOOT_SRC bits are programmed
bit 3
0
0
0
0
0
0
0
0
1
Several boot modes are available depending on the values of the OTP bits BOOT_SRC. If
the OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is
determined by the states of the boot pins P2_8, P1_2, and P1_1.
Table 5.
Boot mode
UART
SPIFI
EMC 8-bit
EMC 16-bit
EMC 32-bit
•
•
BOOT_SRC
bit 2
0
0
0
0
1
1
1
1
0
Secure booting from an encrypted image. In development mode booting from a plain
text image is possible. Development mode is terminated by programming the AES
key.
API for AES programming.
Boot mode when OPT BOOT_SRC bits are zero
All information provided in this document is subject to legal disclaimers.
BOOT_SRC
bit 1
0
0
1
1
0
0
1
1
0
P2_7
HIGH
HIGH
HIGH
HIGH
HIGH
Rev. 1.2 — 17 February 2011
P2_8
LOW
LOW
LOW
LOW
HIGH
BOOT_SRC
bit 0
0
1
0
1
0
1
0
1
0
P1_2
LOW
LOW
HIGH
HIGH
LOW
Description
Boot source is defined by the reset state of P1_1,
P1_2, and P2_8 pins. See
Boot from device connected to USART0 using pins
P2_0 and P2_1.
Boot from Quad SPI flash connected to the SPIFI
interface using pins P3_3 to P3_8.
Boot from external static memory (such as NOR
flash) using CS0 and an 8-bit data bus.
Boot from external static memory (such as NOR
flash) using CS0 and a 16-bit data bus.
Boot from external static memory (such as NOR
flash) using CS0 and a 32-bit data bus.
Boot from USB0.
Boot from USB1.
Boot from SPI flash connected to the SSP0
interface on P3_3, P3_6, P3_7 and P3_8
P1_1
LOW
HIGH
LOW
HIGH
LOW
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
Description
Boot from device connected to USART0
using pins P2_0 and P2_1.
Boot from Quad SPI flash connected to
the SPIFI interface on P3_3 to P3_8
Boot from external static memory (such
as NOR flash) using CS0 and an 8-bit
data bus.
Boot from external static memory (such
as NOR flash) using CS0 and a 16-bit
data bus.
Boot from external static memory (such
as NOR flash) using CS0 and a 32-bit
data bus.
Table
© NXP B.V. 2011. All rights reserved.
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