LPC1850FET256,551 NXP Semiconductors, LPC1850FET256,551 Datasheet - Page 25

• Manufacturer Part Number: LPC1850FET256,551
• Description: MCU 32BIT ARM CORTEX M3 256BGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1850FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, QEI, SD/MMC, SPI, SSI, SSP, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 200K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Processor Series: LPC1850
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 200 KB
• Interface Type: SPI Flash (SPIFI), USB, Ethernet, LCD, External Memory Controller, I2C
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 6
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6682

NXP Semiconductors
Table 3.
LPC1850_30_20_10
Objective data sheet
Symbol
PE_15
PF_0
PF_1
PF_2
PF_3
PF_4
PF_5
PF_6
PF_7
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
Pin description
E13
D12
E11
D11
E10
D10
E9
E7
B7
…continued
Reset
state
[1]
I; PU
I;IA
I; PU
I; PU
I; PU
I;IA
I; PU
I; PU
I; PU
Type Description
-
O
I/O
O
I/O
-
-
-
-
-
I/O
-
-
O
I/O
-
-
I
I/O
-
I/O
I
O
-
-
I/O
I/O
O
-
I/O
I/O
O
-
I/O
I/O
O
All information provided in this document is subject to legal disclaimers.
n.c.
CTOUT_0 — SCT output 0. Match output 0 of timer 0.
I2C1_SCL — I
pad).
EXTBUS_CKEOUT3 — SDRAM clock enable 3.
SSP0_SCK — Serial clock for SSP0.
n.c.
n.c.
n.c.
n.c.
n.c.
SSP0_SSEL — Slave Select for SSP0.
n.c.
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U3_TXD — Transmitter output for USART3.
SSP0_MISO — Master In Slave Out for SSP0.
n.c.
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U3_RXD — Receiver input for USART3.
SSP0_MOSI — Master Out Slave in for SSP0.
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SSP1_SCK — Serial clock for SSP1.
GP_CLKIN — General purpose clock input to the CGU.
TRACECLK — Trace clock.
n.c.
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U3_UCLK — Serial clock input/output for USART3 in synchronous mode.
SSP1_SSEL — Slave Select for SSP1.
TRACEDATA[0] — Trace data, bit 0.
n.c.
U3_DIR — RS-485/EIA-485 output enable/direction control for USART3.
SSP1_MISO — Master In Slave Out for SSP1.
TRACEDATA[1] — Trace data, bit 1.
n.c.
U3_BAUD — <tbd> for USART3.
SSP1_MOSI — Master Out Slave in for SSP1.
TRACEDATA[2] — Trace data, bit 2.
Rev. 1.2 — 17 February 2011
2
C1 clock input/output (this pin does not use a specialized I
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
© NXP B.V. 2011. All rights reserved.
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C