PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 92

• Manufacturer Part Number: PSB21373HV1.1XT
• Manufacturer: Infineon Technologies

Specifications of PSB21373HV1.1XT

• Lead Free Status / RoHS Status: Compliant

Figure 48 gives an example of an interrupt controlled reception sequence, supposed
that a long frame (68 byte) followed by two short frames (12 byte each) is received. The
FIFO threshold (block size) is set to 32 byte (EXMR.RFBS = ’00’) in this example:
• After 32 bytes of frame 1 have been received an RPF interrupt is generated to indicate
• The host reads the first data block from RFIFO and acknowledges the reception by
• The second 32 byte block is indicated by RPF which is read and acknowledged by the
• The reception of the remaining 4 bytes plus RSTA are indicated by RME.
• The host gets the number of received bytes (COUNT = 5) from RBCL/RBCH and
• The second frame is received and indicated by RME interrupt.
• The host gets the number of bytes (COUNT = 13) from RBCL/RBCH and reads out
• The third frame is transferred in the same way.
Figure 48
Reception Sequence, Example
Data Sheet
Receive
Frame
that a data block can be read from the RFIFO.
RMC. Meanwhile the second data block is received and stored in RFIFO.
host as described before.
reads out the RFIFO. The frame is acknowledged by RMC.
the RFIFO. The RFIFO is acknowledged by RMC.
32
RPF
32 Bytes
RD
Bytes
32
68
RMC
RPF
4
32 Bytes
Bytes
RD
12
12
RMC
Bytes
12
12
RME
Count
RD
CPU Interface
IOM Interface
*
5 Bytes
1)
92
RD
The last byte contains the receive status information <RSTA>
*
1)
RMC
RME
Count
RD
13 Bytes
RD
*
1)
RMC RME
Count
RD
PSB 21373
13 Bytes
2002-05-13
fifoseq_rec
RD
*
1)
RMC