PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 30

• Manufacturer Part Number: PSB21373HV1.1XT
• Manufacturer: Infineon Technologies

Specifications of PSB21373HV1.1XT

• Lead Free Status / RoHS Status: Compliant

PSB 21373
Five interrupt bits in the ISTA register point at interrupt sources in the HDLC Controller
(HDLC), Monitor- (MOS) and C/I- (CIC) handler, the transceiver (TRAN) and the
synchronous transfer (ST). The timer interrupt (TIN) and the watchdog timer overflow
(WOV) can be read directly from the ISTA register. All these interrupt sources are
described in the corresponding chapters. After the SCOUT-DX has requested an
interrupt by setting its INT pin to low, the host must read first the SCOUT-DX interrupt
status register (ISTA) in the associated interrupt service routine. The INT pin of the
SCOUT-DX remains active until all interrupt sources are cleared by reading the
corresponding interrupt register. Therefore it is possible that the INT pin is still active
when the interrupt service routine is finished.
Each interrupt indication of the interrupt status registers can selectively be masked by
setting the respective bit in the MASK register.
For some interrupt controllers or hosts it might be necessary to generate a new edge on
the interrupt line to recognize pending interrupts. This can be done by masking all
interrupts at the end of the interrupt service routine (writing FF
into the MASK register)
H
and write back the old mask to the MASK register.
Data Sheet
30
2002-05-13