PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 36

• Manufacturer Part Number: PSB21373HV1.1XT
• Manufacturer: Infineon Technologies

Specifications of PSB21373HV1.1XT

• Lead Free Status / RoHS Status: Compliant

2.2.2.1
The IOM-2 handler provides with his four controller data access registers (CDA10,
CDA11, CDA20, CDA21) a very flexible solution for the access to the 12
IOM-2 time slots by the microcontroller.
The functional unit CDA (controller data access) allows with its control and configuration
registers
• looping of up to four independent PCM channels from DU to DD or vice versa over the
• shifting or switching of two independent PCM channels to another two independent
• monitoring of up to four time slots on the IOM-2 interface simultaneously
• microcontroller read and write access to each PCM channel
The access principle which is identical for the two channel register pairs CDA10/11 and
CDA20/21 is illustrated in figure 13. The index variables x,y used in the following
description can be 1 or 2 for x, and 0 or 1 for y. The prefix ’CDA_’ from the register names
has been omitted for simplification.
To each of the four CDAxy data registers a TSDPxy register is assigned by which the
time slot and the data port can be determined. With the TSS (Time Slot Selection) bits a
time slot from 0...11 can be selected. With the DPS (Data Port Selection) bit the output
of the CDAxy register can be assigned to DU or DD respectively. The time slot and data
port for the output of CDAxy is always defined by its own TSDPxy register. The input of
CDAxy depends on the SWAP bit in the control registers CRx.
If the SWAP bit = ’0’ the time slot and data port for the input and output of the CDAxy
register is defined by its own TSDPxy register. The data port for the CDAxy input is vice
versa to the output setting for CDAxy.
If the SWAP bit = ’1’, the input port and time slot of the CDAx0 is defined by the TSDP
register of CDAx1 and the input port and time slot of CDAx1 is defined by the TSDP
register of CDAx0.
The input and output of every CDAxy register can be enabled or disabled by setting the
corresponding EN (-able) bit in the control register CDAx_CR. If the input of a register is
disabled the output value in the register is retained.
Data Sheet
four CDA registers
PCM channels on both data ports (DU, DD)
Controller Data Access (CDA)
36
PSB 21373
2002-05-13