PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 157

• Manufacturer Part Number: PSB21373HV1.1XT
• Manufacturer: Infineon Technologies

Specifications of PSB21373HV1.1XT

• Lead Free Status / RoHS Status: Compliant

Data Sheet
5
Figure 73 shows the clock system of the SCOUT-DX. The oscillator is used to generate
a 15.36 MHz clock signal. The DPLL generates the IOM-2 clocks FSC (8 kHz), DCL
(1536 kHz) and BCL (768 kHz) synchronous to the received frames of the line interface.
The prescaler for the microcontroller clock output (MCLK) divides the 15.36 MHz clock
by 1, 2 and 8 corresponding to the MCLK control bits in the MODE1 register. Additionally
it is possible to disable the MCLK output by setting the MCLK bits to’11’. With the CDS
bit (Clock Divider Selection) in the MODE1 register a double clock rate for the MCLK
output can be selected.
.
Figure 73
Clock System of the SCOUT-DX
15.36 MHz
Clock Generation
XTAL
MODE1.CDS =
'0': x = 2
'1': x = 1
OSC
15.36 MHz
x
MODE1.MCLK
C/I change
EAW
Watchdog
'00':
'01':
'10':
'11':
DPLL
Reset Generation
MCLK Prescaler
157
2
8
1
MCLK disabled
CPLL
3
FSC
DCL
BCL
Codec
Clock
125 µs < t < 250 µs
125 µs < t < 250 µs
t = 125 µs
MCLK
clock_gen_d
PSB 21373
2002-05-13