PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 191

• Manufacturer Part Number: PSB21373HV1.1XT
• Manufacturer: Infineon Technologies

Specifications of PSB21373HV1.1XT

• Lead Free Status / RoHS Status: Compliant

Data Sheet
7.2.9
Value after reset: 7F
MASK
For the MASK register following logical states are applied:
0: Interrupt is not masked
1: Interrupt is masked
Each interrupt source in the ISTA register can be selectively masked by setting to ’1’ the
corresponding bit in MASK. Masked interrupt status bits are not indicated when ISTA is
read. Instead, they remain internally stored and pending, until the mask bit is reset to ’0’.
Note: In the event of a C/I channel change, CIC is set in ISTA even if the corresponding
7.2.10
Value after reset: 00
MODE1
MCLK
The Master Clock Frequency bits control the microcontroller clock output corresponding
following table.
Bit 7
0
0
1
1
mask bit in MASK is active, but no interrupt is generated.
MASK - Mask Register
7
MODE1 - Mode1 Register
7
Bit 6
0
1
0
1
0
MCLK
... Master Clock Frequency
H
H
ST
MCLK frequency
with
MODE1.CDS = ’0’
3.84 MHz
0.96 MHz
7.68 MHz
disabled
CDS WTC1 WTC2
CIC
TIN
191
WOV TRAN MOS HDLC
CFS
MCLK frequency
with
MODE1.CDS = ’1’
7.68 MHz
1.92 MHz
15.36 MHz
disabled
RSS2 RSS1 RD/WR (3D
0
0
PSB 21373
2002-05-13
WR (3C
H
H
)
)