PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 192

• Manufacturer Part Number: PSB21373HV1.1XT
• Manufacturer: Infineon Technologies

Specifications of PSB21373HV1.1XT

• Lead Free Status / RoHS Status: Compliant

CDS
0: The 15.36 MHz oscillator clock divided by two is input to the MCLK prescaler
1: The 15.36 MHz oscillator clock is input to the MCLK prescaler.
WTC1, 2
If the watchdog timer is enabled (RSS = ’11’) the microcontroller has to program the
WTC1 and WTC2 bit within each time period of 128 ms in the following sequence:
(See chapter 6.1).
CFS
This bit determines clock relations and recovery on the line and IOM interfaces
0: The IOM interface clock and frame signals are always active,
1: The IOM interface clock and frame signals are normally inactive ("Power Down").
Note:After reset the IOM interface is always active. To reach the "Power Down" state the
Data Sheet
"Power Down" state included.
The states "Power Down" and "Power Up" are thus functionally identical except for
the indication: PD = 1111 and PU = 0111.
With the C/I command Timing (TIM) the microcontroller can enforce the
"Power Up" state.
With C/I command Deactivation Indication (DI) the "Power Down" state is
reached again.
It is also possible to activate the line Interface directly with the
C/I command Activate Request (AR) without the TIM command.
For activating the IOM-2 clocks the "Power Up" state can be induced by software
(SPU-bit in SPCR register) or by resetting again CFS.
After that the line interface can be activated with the C/I command Activate Request
(AR ). The "Power Down" state can be reached again with the C/I command
Deactivation Indication (DI).
CFS-bit has to be set.
1.
2.
... Clock Divider Selection
... Watchdog Timer Control 1, 2
... Configuration Select
WTC1
1
0
WTC2
0
1
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PSB 21373
2002-05-13