PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 73

• Manufacturer Part Number: PSB21373HV1.1XT
• Manufacturer: Infineon Technologies

Specifications of PSB21373HV1.1XT

• Lead Free Status / RoHS Status: Compliant

Data Sheet
2.3.4.1.3
Command (Upstream)
Timing
Reset
Send Single Pulses
Send Continuous Pulses
Activate Request
Activate Request Loop 3
Deactivation Indication
2.3.4.1.4
Name
Info 0
Info 2
Info 4
Info X
2.3.4.1.5
RES
A low signal on the RST pin or setting the RES_TR bit in the SRES register to
’1’ resets also the layer-1 state machine. The reset signals should be applied
for a minimum of 2 DCL clock cycles. The function of these reset events is
identical to the C/I code RES concerning the state machine.
C/I Commands
Receive Infos on the Line (Downstream)
Reset
Abbr. Description
i0
i2
i4
ix
Abbr. Code Remarks
TIM
RES
SSP
SCP
AR
ARL
Dl
No signal on the line
4-kHz burst signal
F=’1’
B1-, B2- and D- channels are scrambled ’1’s.
4-kHz burst signal
F=’1’
B1-, B2- and D- channels are scrambled data.
Any signal except info 2 or info 4
0000 Layer-2 device requires clocks to be
0001 State machine reset
0010 AMI coded pulses transmitted at 4 kHz
0011 AMI coded pulses transmitted
1000
1001 Local analog loop
1111
73
activated
continuously
PSB 21373
2002-05-13