PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 161

• Manufacturer Part Number: PSB21373HV1.1XT
• Manufacturer: Infineon Technologies

Specifications of PSB21373HV1.1XT

• Lead Free Status / RoHS Status: Compliant

Data Sheet
6.2
At the active low RST input pin an external reset can be applied forcing the device into
the reset state. This external reset signal is additionally fed to the RSTO/SDS2 output.
The length of the reset signal is specified in chapter 8.1.8.
After an external reset (RST) all internal registers are set to their reset values (see
register description in chapter 7).
6.3
Every internal functional block can be reset separately by setting the corresponding bit
in the SRES register (see chapter 7.2.13). The reset state is activated as long as the bit
is set to’1’. The address range of the registers which will be reset at each SRES bit is
listed in figure 75.
6.4
During each reset the reference voltage (V
clocks (DCL) keep running.
In all cases the microcontroller clock is running.
During any reset that has an influence on the IOM handler (see figure 75) the pin FSC
is set to’1’, the pin SDS1 is set to’0’ and pin BCL, DD and DU are in the high-impedance
state.
During any reset that has an influence on the codec (see figure 75) the pins LSP, LSN,
HOP and HON are in the high-impedance state.
During any reset that has an influence on the transceiver (see figure 75) the pins Via
and LIb are in the high-impedance state.
During hardware reset the pins SDX and INT are in the high-impedance state.
A hardware reset is always output at pin RSTO/SDS2. This reset will be released by the
falling edge of BCL following the release of the pin RST.
External Reset Input
Software Reset Register (SRES)
Pin Behavior during Reset
161
REF
) stays applied, the oscillator and data
PSB 21373
2002-05-13