PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 101

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PSB21373HV1.1XT

Manufacturer Part Number
PSB21373HV1.1XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB21373HV1.1XT

Lead Free Status / RoHS Status
Compliant
Data Sheet
3.5
This non-HDLC mode is selected by setting MODE2...0 to ’100’. In extended transparent
mode fully transparent data transmission/reception without HDLC framing is performed
i.e. without FLAG generation/recognition, CRC generation/check, bit stuffing
mechanism. This allows user specific protocol variations.
3.5.1
The transmitter sends the data out of the FIFO without manipulation. Transmission is
always IOM-frame aligned and byte aligned, i.e. transmission starts in the first selected
channel (B1, B2, D, according to the setting of register HCI_CR in the IOM Handler) of
the next IOM frame.
The FIFO indications and commands are the same as in other modes.
If the microcontroller sets XTF & XME the transmitter responds with an XPR interrupt
after sending the last byte, then it returns to its idle state (sending continuous ‘1’).
If the collision detection is enabled (MODE.DIM = ’0x1’) the stop go bit (S/G) can be used
as clear to send indication as in any other mode. If the S/G bit is set to ’1’ (stop) during
transmission the transmitter responds always with an XMR (transmit message repeat)
interrupt.
If the microcontroller fails to respond to a XPR interrupt in time and the transmitter runs
out of data then it will assert an XDU (transmit data underrun) interrupt.
3.5.2
The reception is IOM-frame aligned and byte aligned, like transmission, i.e. reception
starts in the first selected channel (B1, B2, D, according to the setting of register HCI_CR
in the IOM Handler) of the next IOM frame. The FIFO indications and commands are the
same as in others modes.
All incoming data bytes are stored in the RFIFO and additionally made available in
RSTA. If the FIFO is full an RFO interrupt is asserted (EXMR.SRA = ’0’).
Note: In the extended transparent mode the EXMR register has to be set to ’xxx00000’
Extended Transparent Mode
Transmitter
Receiver
101
PSB 21373
2002-05-13

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