PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 59

• Manufacturer Part Number: PSB21373HV1.1XT
• Manufacturer: Infineon Technologies

Specifications of PSB21373HV1.1XT

• Lead Free Status / RoHS Status: Compliant

Data Sheet
consecutive codes are detected, only the first and the last code is obtained at the first
and second register read, respectively.
For CIR1 no FIFO is available. The actual code of the received C/I channel 1 is always
stored in CIR1.
Figure 28
CIC Interrupt Structure
2.2.6
After reset the codec, the TIC-bus access, the serial data strobes (pin SDS1 and SDS2)
and the controller data access are disabled.
The IOM handler is enabled except the generation of the bit clock (pin BCL).
The monitor handler is enabled for channel MON0 and the transceiver for the channels
B1, B2, C/I0 and D.
The HDLC controller is connected to the D channels.
The pins DD and DU are in open drain state.
The synchronous transfer interrupts and synchronous transfer overflow interrupts are
masked.
Settings after Reset (see also chapter 7.3)
TRAN
MASK
HDLC
WOV
MOS
CIC
TIN
INT
ST
TRAN
HDLC
ISTA
WOV
MOS
CIC
TIN
ST
59
CI1E
CIX1
CIC0
CIC1
CIR0
PSB 21373
2002-05-13