PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 100

• Manufacturer Part Number: PSB21373HV1.1XT
• Manufacturer: Infineon Technologies

Specifications of PSB21373HV1.1XT

• Lead Free Status / RoHS Status: Compliant

3.3.2
The transmission of transparent frames (XTF command) is shown in figure 52.
For transparent frames, the whole frame including address and control field must be
written to the XFIFO. The host configures whether the CRC is generated and appended
to the frame (default) or not (selected in EXMR.XCRC).
Furthermore, the host selects the interframe time fill signal which is transmitted between
HDLC frames (EXMR:ITF). One option is to send continuous flags (’01111110’),
however if D-channel access handling is required, the signal must be set to idle
(continuous ’1’s are transmitted).
Figure 52
Transmit Data Flow
3.4
By setting the enable HDLC data bits (EN_D, EN_B1H, EN_B2H) in the HCI_CR register
the HDLC controller can access the D, B1, B2 channels or the combination of them (e.g.
18 bit IDSL data (2B+D)). In all modes sending works always frame aligned, i.e. it starts
with the first selected channel whereas reception looks for a flag anywhere in the serial
data stream.
Data Sheet
Transmit Transparent Frame
*
1)
The CRC is generated by default.
If EXMR.XCRC is set no CRC is appended
Transmit Frame Structure
Access to IOM Channels
(XTF)
FLAG
ADDRESS
ADDR
100
XFIFO
CONTROL DATA
CTRL
I
CHECKRAM
CRC
*
1)
fifoflow_tran
PSB 21373
FLAG
2002-05-13