MC9S08AW60CFGE Freescale, MC9S08AW60CFGE Datasheet - Page 95

• Manufacturer Part Number: MC9S08AW60CFGE
• Manufacturer: Freescale

Specifications of MC9S08AW60CFGE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

1
1
6.7.6
In addition to the I/O control, port C pins are controlled by the registers listed below.
Freescale Semiconductor
PTCDD[5:0]
PTCPE[5:0]
Bit 6 is a reserved bit that must always be written to 0.
Bit 6 is a reserved bit that must always be written to 0.
Reset
Reset
Field
Field
5:0
5:0
W
W
R
R
Port C Pin Control Registers (PTCPE, PTCSE, PTCDS)
Data Direction for Port C Bits — These read/write bits control the direction of port C pins and what is read for
PTCD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn.
Internal Pullup Enable for Port C Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTC pin. For port C pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port C bit n.
1 Internal pullup device enabled for port C bit n.
0
0
0
0
7
7
Figure 6-22. Internal Pullup Enable for Port C (PTCPE)
R
R
0
0
6
6
Figure 6-21. Data Direction for Port C (PTCDD)
Table 6-12. PTCDD Register Field Descriptions
Table 6-13. PTCPE Register Field Descriptions
PTCDD5
PTCPE5
MC9S08AC16 Series Data Sheet, Rev. 8
0
0
5
5
PTCDD4
PTCPE4
0
0
4
4
Description
Description
PTCDD3
PTCPE3
3
0
3
0
PTCDD2
PTCPE2
0
0
2
2
1
1
Chapter 6 Parallel Input/Output
PTCDD1
PTCPE1
0
0
1
1
PTCDD0
PTCPE0
0
0
0
0
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