MC9S08AW60CFGE Freescale, MC9S08AW60CFGE Datasheet - Page 83

• Manufacturer Part Number: MC9S08AW60CFGE
• Manufacturer: Freescale

Specifications of MC9S08AW60CFGE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

6.2
Parallel I/O and Pin Control features, depending on package choice, include:
6.3
The MC9S08AC16 Series has a total of 38 parallel I/O pins in seven ports (PTA–PTG). Not all pins are
bonded out in all packages. Consult the pin assignment in
parallel I/O pins. All of these pins are available for general-purpose I/O when they are not used by other
on-chip peripheral systems.
After reset, the shared peripheral functions are disabled so that the pins are controlled by the parallel I/O.
All of the parallel I/O are configured as inputs (PTxDDn = 0). The pin control functions for each pin are
configured as follows: slew rate control enabled (PTxSEn = 1), low drive strength selected (PTxDSn = 0),
and internal pullups disabled (PTxPEn = 0).
The following paragraphs discuss each port and the software controls that determine each pin’s use.
6.3.1
Port A pins are general-purpose I/O pins. Parallel I/O function is controlled by the port A data (PTAD) and
data direction (PTADD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTAPE), slew rate control (PTASE), and drive strength select (PTADS) are located in the
high page registers. Refer to
general-purpose I/O control and
Freescale Semiconductor
Port A
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•
•
•
•
•
•
•
•
•
•
A total of 38 general-purpose I/O pins in seven ports
Hysteresis input buffers
Software-controlled pullups on each input pin
Software-controlled slew rate output buffers
Four port A pins
Four port B pins shared with ADC1 and TPM3
Six port C pins shared with SCI2, IIC1, and MCLK
Four port D pins shared with ADC1, KBI, and TPM1 and TPM2 external clock inputs
Eight port E pins shared with SCI1, TPM1, and SPI1
Five port F pins shared with TPM1 and TPM2
Seven port G pins shared with XTAL, EXTAL, and KBI
Features
Pin Descriptions
Port A
MCU Pin:
PTA7
Bit 7
Section 6.4, “Parallel I/O
Section 6.5, “Pin
MC9S08AC16 Series Data Sheet, Rev. 8
R
6
Figure 6-2. Port A Pin Names
R
5
Control” for more information about pin control.
Control” for more information about
Chapter 2, “Pins and
R
4
R
3
PTA2
2
Connections,” for available
Chapter 6 Parallel Input/Output
PTA1
1
PTA0
Bit 0
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