MC9S08AW60CFGE Freescale, MC9S08AW60CFGE Datasheet - Page 50

• Manufacturer Part Number: MC9S08AW60CFGE
• Manufacturer: Freescale

Specifications of MC9S08AW60CFGE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

Chapter 4 Memory
When security is enabled, the RAM is considered a secure memory resource and is not accessible through
BDM or through code executing from non-secure memory. See
description of the security feature.
4.4
The FLASH memory is intended primarily for program storage. In-circuit programming allows the
operating program to be loaded into the FLASH memory after final assembly of the application product.
It is possible to program the entire array through the single-wire background debug interface. Because no
special voltages are needed for FLASH erase and programming operations, in-application programming
is also possible through other software-controlled communication paths. For a more detailed discussion of
in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I,
Freescale Semiconductor document order number HCS08RMv1/D.
4.4.1
Features of the FLASH memory include:
4.4.2
Before any program or erase command can be accepted, the FLASH clock divider register (FCDIV) must
be written to set the internal clock for the FLASH module to a frequency (f
200 kHz (see
once, so normally this write is done during reset initialization. FCDIV cannot be written if the access error
flag, FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the
FCDIV register. One period of the resulting clock (1/f
program and erase pulses. An integer number of these timing pulses are used by the command processor
to complete a program or erase command.
Table 4-5
of FCLK (f
of cycles of FCLK and as an absolute time for the case where t
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
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FLASH Size
— MC9S08AC16 and MC9S08AW16A— 16,384 bytes (32 pages of 512 bytes each)
— MC9S08AC8 and MC9S08AW8A— 8192 bytes (16 pages of 512 bytes each)
Single power supply program and erase
Command interface for fast program and erase operation
Up to 100,000 program/erase cycles at typical voltage and temperature
Flexible block protection
Security feature for FLASH and RAM
Auto power-down for low-frequency read accesses
FLASH
shows program and erase times. The bus clock frequency and FCDIV determine the frequency
Features
Program and Erase Times
FCLK
Section 4.6.1, “FLASH Clock Divider Register
). The time for one cycle of FCLK is t
MC9S08AC16 Series Data Sheet, Rev. 8
FCLK
FCLK
) is used by the command processor to time
= 1/f
(FCDIV)”). This register can be written only
FCLK
Section 4.5,
FCLK
= 5 μs. Program and erase times
. The times are shown as a number
FCLK
“Security” for a detailed
) between 150 kHz and
Freescale Semiconductor