MC9S08AW60CFGE Freescale, MC9S08AW60CFGE Datasheet - Page 161

• Manufacturer Part Number: MC9S08AW60CFGE
• Manufacturer: Freescale

Specifications of MC9S08AW60CFGE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

10.3
The TPMV3 is the latest version of the Timer/PWM module that addresses errata found in previous
versions. The following section outlines the differences between TPMV3 and TPMV2 modules, and any
considerations that should be taken when porting code.
Freescale Semiconductor
Write to TPMxCnTH:L registers
Any write to TPMxCNTH or TPMxCNTL registers
Read of TPMxCNTH:L registers
In BDM mode, any read of TPMxCNTH:L registers
In BDM mode, a write to TPMxSC, TPMxCNTH or TPMxCNTL Clears this read coherency
Read of TPMxCnVH:L registers
In BDM mode, any read of TPMxCnVH:L registers
In BDM mode, a write to TPMxCnSC
Write to TPMxCnVH:L registers
In Input Capture mode, writes to TPMxCnVH:L registers
In Output Compare mode, when (CLKSB:CLKSA not = 0:0),
writes to TPMxCnVH:L registers
TPMV3 Differences from Previous Versions
Action
Table 10-1. TPMV2 and TPMV3 Porting Considerations
3
1
2
1
MC9S08AC16 Series Data Sheet, Rev. 8
3
Clears the TPM counter
(TPMxCNTH:L) and the
prescaler counter.
Returns the value of the TPM
counter that is frozen.
mechanism.
Returns the value of the
TPMxCnVH:L register.
Clears this read coherency
mechanism.
Not allowed.
Update the TPMxCnVH:L
registers with the value of
their write buffer at the next
change of the TPM counter
(end of the prescaler
counting) after the second
byte is written.
TPMV3
Chapter 10 Timer/PWM (S08TPMV3)
Clears the TPM counter
(TPMxCNTH:L) only.
If only one byte of the
TPMxCNTH:L registers was
read before the BDM mode
became active, returns the
latched value of TPMxCNTH:L
from the read buffer (instead of
the frozen TPM counter value).
Does not clear this read
coherency mechanism.
If only one byte of the
TPMxCnVH:L registers was
read before the BDM mode
became active, returns the
latched value of TPMxCNTH:L
from the read buffer (instead of
the value in the TPMxCnVH:L
registers).
Does not clear this read
coherency mechanism.
Allowed.
Always update these registers
when their second byte is
written.
TPMV2
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