MC9S08AW60CFGE Freescale, MC9S08AW60CFGE Datasheet - Page 75

• Manufacturer Part Number: MC9S08AW60CFGE
• Manufacturer: Freescale

Specifications of MC9S08AW60CFGE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

5.9.5
This register is used to control the MCLK clock output.
5.9.6
This read-only register is included so host development systems can identify the HCS08 derivative and
revision number. This allows the development software to recognize where specific memory blocks,
registers, and control bits are located in a target MCU.
Freescale Semiconductor
Reserved
Reset
Reset
MCSEL
ID[11:8]
Field
Field
MPE
2:0
7:4
3:0
4
W
W
R
R
System MCLK Control Register (SMCLK)
System Device Identification Register (SDIDH, SDIDL)
MCLK Pin Enable — This bit is used to enable the MCLK function.
0 MCLK output disabled.
1 MCLK output enabled on PTC2 pin.
MCLK Divide Select — These bits are used to select the divide ratio for the MCLK output according to the
formula below when the MCSEL bits are not equal to all zeroes. In the case that the MCSEL bits are all zero and
MPE is set, the pin is driven low. See
Bits 7:4 are reserved. Reading these bits will result in an indeterminate value; writes have no effect.
Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The
MC9S08AC16 Series is hard coded to the value 0x012. See also ID bits in
—
0
0
7
7
Figure 5-7. System Device Identification Register — High (SDIDH)
= Unimplemented or Reserved
= Unimplemented or Reserved
—
0
0
6
6
Figure 5-6. System MCLK Control Register (SMCLK)
MCLK frequency = Bus Clock frequency ÷ (2 * MCSEL)
Table 5-7. SMCLK Register Field Descriptions
Table 5-8. SDIDH Register Field Descriptions
MC9S08AC16 Series Data Sheet, Rev. 8
—
0
0
5
5
Equation
MPE
—
0
4
4
5-1.
Description
Description
ID11
Chapter 5 Resets, Interrupts, and System Configuration
3
0
0
3
0
ID10
0
0
2
2
Table
5-9.
MCSEL
ID9
0
0
1
1
Eqn. 5-1
ID8
0
0
0
0
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