NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 88

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
4.5.3.
4.5.4.
88
®
82810E (GMCH)
Address Translation
Display Cache Interface Timing
The GMCH contains address decoders that translate the address received by the display cache into an
effective display cache address. The LMA[11:0] bits are as defined below. Entries in the table
(e.g., A21(X)) imply that the GMCH puts out A21 on that MA line but it is not used by the SDRAM.
Note: BA = Bank address
The GMCH provides a variety of programmable wait states for DRAM read and write cycles. These
options are programmed in the display cache I/O addresses of the GMCH configuration space. The wrap
type and the burst length is implied since they are not programmable and fixed. Only sequential wrap is
allowed. Burst length is fixed at two.
11(BA)
10
9
8
7
6
5
4
3
2
1
0
MA
GMCH Local Memory Address
Row
A10
A11
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
Mapping
1Mx16
Column
A10
X
X
X
A9
A8
A7
A6
A5
A4
A3
A2
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