NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 42

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
3.4.17.
42
®
82810E (GMCH)
FCHC    Fixed DRAM Hole Control Register (Device 0)
Offset:
Default:
Access:
Size:
This 8-bit Register Controls 1 fixed DRAM holes: 15–16MB.
7
6:0
Bit
Bit
7
1
0
Enable
Hole
Hole Enable (HEN)—RW. This Bit enables a memory hole in DRAM space. Host cycles matching a
enabled hole are passed on to the ICH through the Hub Interface. Hub Interface cycles matching an
enabled hole will be ignored by the GMCH. Note that the hole is not re-mapped
0 = Disabled (Default)
1 = Enabled (15MB–16MB; 1MB size)
Reserved
SDRAM RAS# to CAS# Delay (SRCD). This bit controls the number of SCLKs from a Row Activate
command to a read or write command.
0 = 3 SCLKs (Default)
1 = 2 SCLKs
SDRAM RAS# Precharge (SRP). This bit controls the number of SCLKs for RAS# precharge.
0 = 3 SCLKs (Default)
1 = 2 SCLKs
6
58h
00h
Read/Write
8 bits
Description
Description
Reserved
Datasheet
0
R