NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 113

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

6.2.
6.2.1.
6.2.2.
Datasheet
R
Chain [1:2, 4:7] Initialization
Chain 3 Initialization
XOR Tree Initialization
On chains [1:2,4:7], all that is required to prepare the device for XOR chain testing is to pull LMD31
high (+3.3V) prior to the deasserting RESET#. LMD31 must be brought back to a low state after this
sequence, as this pin is part of XOR chain 2. The following sequence will put the GMCH into XOR
testability mode:
No external clocking of the GMCH is required for testing these chains.
To test XOR chain 3, a different initialization sequence is required. The following steps need to be
implemented:
1. Deassert RESET# high and LMD31 (high)
2. Assert RESET# low; maintain LMD31 (high)
3. Deassert RESET# high; maintain LMD31 (high)
4. RESET# must be maintained high for the duration of testing.
1. Provide clocks at a minimum frequency of 10 MHz to the GMCH host clock (HCLK), hub
2. Deassert RESET# high and assert LMD31 high
3. Assert RESET# low for 35,000 HLCLKs; maintain LMD31 high
4. Deassert RESET# high for 35,000 HLCLKs; maintain LMD31 high
5. Chain #3 is now initialized and ready to begin XOR test. RESET# must be maintained high for the
interface clock (HLCLK), and display interface clock (DCLKREF). Phase relationship between
HCLK and HLCLK must be maintained such that they are 180 degrees out of phase, and their
edges line up within 400 pS.
duration of testing.
Intel
®
82810E (GMCH)
113