NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 52

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
3.5.4.
52
®
82810E (GMCH)
PCISTS    PCI Status Register (Device 1)
Address Offset:
Default Value:
Access:
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI
compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the GMCH
hardware.
10:9
6:5
3:0
Bit
15
14
13
12
11
Detected
Par Error
8
7
4
(HW=0)
(HW=1)
FB2B
15
7
Detected Parity Error (DPE)    RO. Since the internal graphics device of the GMCH does not detect
parity, this bit is always set to 0.
Signaled System Error (SSE)    RO. The internal graphics device of the GMCH device never asserts
SERR#, therefore this bit is hardwired to 0.
Received Master Abort Status (RMAS)    RO. The internal graphics device of the GMCH device never
gets a Master Abort, therefore this bit is hardwired to 0.
Received Target Abort Status (RTAS)    RO.. The internal graphics device of the GMCH device never
gets a Target Abort, therefore this bit is hardwired to 0.
Signaled Target Abort Status (STAS). Hardwired to 0. The internal graphics device of the GMCH
does not use target abort semantics.
DEVSEL# Timing (DEVT)    RO. This 2-bit field indicates the timing of the DEVSEL# signal when the
internal graphics device of the GMCH responds as a target. Hardwired to 01 to indicate that the internal
graphics device of the GMCH is a medium decode device.
Data Parity Detected (DPD)    R/WC. Since Parity Error Response is hardwired to disabled (and the
internal graphics device of the GMCH does not do any parity detection), this bit is hardwired to 0.
Fast Back-to-Back (FB2B). Hardwired to 1. The internal graphics device of the GMCH accepts fast
back-to-back when the transactions are not to the same agent.
Reserved.
CAP LIST    RO. This bit is set to 1 to indicate that the register at 34h provides an offset into the
function’s PCI Configuration Space containing a pointer to the location of the first item in the list.
Reserved.
Reserved
Sig Sys
(HW=0)
Error
14
6
Mast Abort
Reserved
(HW=0)
Recog
Sta
13
5
06h−07h
02B0h
Read Only
Abort Sta
Cap List
(HW=0)
(HW=1)
Target
Rec
12
4
Descriptions
3
Sig Target
Abort Sta
(HW=0)
11
10
DEVSEL# Timing
Reserved
(HW=01)
9
Detected
Data Par
(HW=0)
Datasheet
8
0
R