NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 26

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
3.2.
3.2.1.
26
®
82810E (GMCH)
Note: Even though the primary PCI bus is referred to as PCI0 in this document it is not PCI bus #0 from a
PCI Bus Configuration Mechanism
PCI Configuration Space Access
The GMCH and the ICH are physically connected via the hub interface. From a configuration standpoint,
the hub interface connecting the GMCH and the ICH is logically PCI bus #0. All devices internal to the
GMCH and ICH appear to be on PCI bus #0. The system primary PCI expansion bus is physically
attached to the ICH and, from a configuration standpoint, appears as a hierarchical PCI bus behind a
PCI-to-PCI bridge. The primary PCI expansion bus connected to the ICH has a programmable PCI Bus
number.
configuration standpoint.
The GMCH contains two PCI devices within a single physical component. The configuration registers
for both Device 0 and 1 are mapped as devices residing on PCI bus #0.
Note that a physical PCI bus #0 does not exist. The hub interface and the internal devices in the GMCH
and ICH logically constitute PCI Bus #0 to configuration software.
The PCI Bus defines a slot based "configuration space" that allows each device to contain up to 8
functions with each function containing up to 256 8-bit configuration registers. The PCI specification
defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration
Write. Memory and I/O spaces are supported directly by the processor. Configuration space is supported
by a mapping mechanism implemented within the GMCH. The PCI specification defines two
mechanisms to access configuration space, Mechanism #1 and Mechanism #2.
The GMCH supports only Mechanism #1
The configuration access mechanism makes use of the CONFIG_ADDRESS Register and
CONFIG_DATA Register. To reference a configuration register a DWord I/O write cycle is used to
place a value into CONFIG_ADDRESS that specifies the PCI bus, the device on that bus, the function
within the device, and a specific configuration register of the device function being accessed.
CONFIG_ADDRESS[31] must be 1 to enable a configuration cycle. CONFIG_DATA then becomes a
window into the four bytes of configuration space specified by the contents of CONFIG_ADDRESS.
Any read or write to CONFIG_DATA will result in the GMCH translating the CONFIG_ADDRESS into
the appropriate configuration cycle.
The GMCH is responsible for translating and routing the processor I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA registers to internal GMCH configuration registers, the
internal graphic device, or the hub interface.
• Device 0: Host-hub interface Bridge/DRAM Controller. Logically this appears as a PCI device
• Device 1: GMCH internal graphics device. These registers contain the PCI registers for the GMCH
residing on PCI bus #0. Physically Device 0 contains the PCI registers, DRAM registers, and other
GMCH specific registers.
internal graphics device.
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