NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 72

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
72
Table 7. Memory Segments and their Attributes
®
82810E (GMCH)
Table 7 lists the memory segments of interest in the compatibility area. Four of the memory ranges can
be enabled or disabled independently for both read and write cycles. One segment (0DC000h to
0DFFFFh) is conditionally mapped to the PCI Bus (via the hub interface).
000000h–09FFFFh
0A0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0DC000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
• DOS Area (00000h–9FFFFh). The 640 KB DOS area is always mapped to the main memory
• Video Buffer Area (A0000h–BFFFFh). The 128 Kbyte graphics adapter memory region is
• Monochrome Adapter (MDA) Range (B0000h–B7FFFh). SMRAM[GMS bits] (Device #0),
• CD Hole (DC000h–DFFFFh). GMCHCFG[CDHEN] (Device 0) controls the routing of accesses
• BIOS etc Shadow Area (C0000h–FFFFFh). Except for the CD Hole area, access to this range is
controlled by the GMCH.
normally mapped to a legacy video device (e.g., VGA controller) on PCI via the hub interface. This
area is not controlled by the attribute bits and processor-initiated cycles in this region are forwarded
to hub interface or the internal graphics device for termination. This region is also the default region
for SMM space.
Accesses to this range are directed to either PCI (via the hub interface) or the internal graphics
device based on the configuration specified in SMRAM[GMS bits] (GMCH Device #0
configuration register) with additional steering information coming from the Device #1
configuration registers and from some of the VGA registers in the graphics device. The control is
applied for accesses initiated from any of the system interfaces (i.e., host bus or hub interface). For
more details see the descriptions in the configuration registers specified above.
SMRAM controls how SMM accesses to this space are treated.
PCICMD register bits of Device #1, and bits in some of the VGA registers control this functionality.
( see Section 4.1.1.2).
in this region. When CDHEN = 1, all accesses to the address range 000DC000h–000DFFFFh are
forwarded on to PCI, independent of the programming of the PAM register. When CDHEN = 0, the
CD Hole region is controlled by bits [3:2] of the PAM Register.
controlled by the bits of the PAMR register bits.
Memory Segments
fixed - always mapped to main DRAM
mapped to PCI - configurable as SMM
space
R/W, WO, RO, Disabled
R/W, WO, RO, Disabled
Included in above or Disabled
R/W, WO, RO, Disabled
R/W, WO, RO, Disabled
Attributes
0 to 640K - DOS Region
Video Buffer (physical DRAM
configurable as SMM space)
BIOS etc Shadow Area
BIOS etc Shadow Area
BIOS etc Shadow Area, Memory Hole
BIOS etc Shadow Area
BIOS etc Shadow Area
Comments
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