NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 39

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

3.4.15.
Datasheet
R
DRP    DRAM Row Population Register (Device 0)
CD Hole (DC000h–DFFFFh)
This 16 KB area is controlled by 2 sets of attribute bits. Host-initiated cycles in this region are forwarded
to the ICH based upon the programming of PAM[3:2] and the CDHEN bit in the GMCHCFG register.
Video Buffer Area (A0000h–BFFFFh)
This 128 KB area is not controlled by attribute bits. The host-initiated cycles in this region are always
forwarded to either the Graphics device or to the ICH unless this range is accessed in SMM mode.
Routing of these accesses is controlled by the Graphics Mode Select field of the SMRAM register.
This area can be programmed as SMM area via the SMRAM register. This range can not be accessed
from the hub interface.
Address Offset:
Default Value:
Access:
Size:
GMCH supports 4 physical rows of system memory in 2 DIMMs. The width of a row is 64 bits. The
DRAM Row Population Register defines the population of each Side of each DIMM. Note: this entire
register becomes read only when the SMM Space Locked (D_LCK) bit is set in the SMRAMSystem
Management RAM Control Register (offset 70h).
15
Bit
7:4
3:0
DIMM 1 Population. This field indicates the population of DIMM 1. (See table below )
DIMM 0 Population. This field indicates the population of DIMM 0. (See table below )
DIMM 1 Population
52h
00h
Read/Write (read only)
8 bits
4
Description
3
DIMM 0 Population
Intel
®
82810E (GMCH)
0
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