NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 8
NH82810 S L7XK
Manufacturer Part Number
NH82810 S L7XK
Description
Manufacturer
Intel
Datasheet
1.NH82810_S_L7XK.pdf
(119 pages)
Specifications of NH82810 S L7XK
Lead Free Status / RoHS Status
Compliant
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Intel
8
®
82810E (GMCH)
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Intel
Product Features
Processor/Host Bus Support
Integrated DRAM Controller
Integrated Graphics Controller
3D Graphics Visual Enhancements
3D Graphics Texturing Enhancements
Digital Video Output
Display
Optimized for the Intel
Supports processor 370-Pin Socket and SC242
Supports 32-Bit System Bus Addressing
4 deep in-order queue; 4 or 1 deep request queue
Supports Uni-processor systems only
In-order and Dynamic Deferred Transaction
66/100/133 MHz System Bus Frequency
AGTL+ I/O Buffer
8 MB to 256 MB using 16Mb/64Mb technology
Supports up to 2 double sided DIMM modules
64-bit data interface
100 MHz system memory bus frequency
Support for Asymmetrical DRAM addressing only
Support for x8, x16 and x32 DRAM device width
Refresh Mechanism: CBR ONLY supported
Enhanced Open page Arbitration SDRAM paging
Suspend to RAM support
3D Hyper Pipelined Architecture
Full 2D H/W Acceleration
Motion Video Acceleration
Flat & Gouraud Shading
Mip Maps with Bilinear and Anisotropic Filtering
Fogging Atmospheric Effects
Z Buffering
3D Pipe 2D Clipping
Backface Culling
Per Pixel Perspective Correction Texture Mapping
Texture Compositing
Texture Color Keying/Chroma Keying
85 MHz Flat Panel Monitor Interface Or Digital
Integrated 24-bit 230 MHz RAMDAC
Gamma Corrected Video
DDC2B Compliant
Intel
Celeron
connectors
Support
(512 MB using 128Mb technology)
scheme
Video Output for use with a external TV encoder
-Parallel Data Processing (PDP)
-Precise Pixel Interpolation (PPI)
Pentium III processor, and Intel
TM
®
processor
82810E GMCH
Pentium II processor,
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2D Graphics
Arithmetic Stretch Blitter Video
Integrated Graphics Memory Controller
Display Cache Interface
Arbitration Scheme and Concurrency
Data Buffering
Power Management Functions
Supporting I/O Bridge
Packaging/Power
Up to 1600x1200 in 8-bit Color at 75 Hz Refresh
Hardware Accelerated Functions
H/W Motion Compensation Assistance for S/W
Software DVD at 30 fps
Digital Video Out Port
NTSC and PAL TV Out Support
H/W Overlay Engine with Bilinear Filtering
Independent gamma correction, saturation,
Intel
32-bit data interface
100/133 MHz SDRAM interface
Support for 1Mx16, (4 MB Only)
Centralized Arbitration Model for Optimum
Concurrent operations of processor and system
Distributed Data Buffering Model for optimum
DRAM Write Buffer with read-around-write
Dedicated processor -DRAM, hub interface-
SMRAM space remapping to A0000h (128 KB)
Optional Extended SMRAM space above
Stop Clock Grant and Halt special cycle translation
ACPI Compliant power management
APIC Buffer Management
SMI, SCI, and SERR error indication
241 Pin BGA I/O Controller Hub ICH
421 BGA
1.8V core with 3.3V CMOS I/O
MPEG2 Decode
brightness & contrast for overlay
Concurrency Support
busses supported via dedicated arbitration and data
buffering
concurrency
capability
DRAM and Graphics-DRAM Read Buffers
256 MB, additional 512K/1MB TSEG from Top of
Memory, cacheable
from the host to the hub interface
3 Operand Raster BitBLTs
64x64x3 Color Transparent Cursor
D.V.M. Technology
Datasheet
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