NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 23

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

2.7.
2.8.
Datasheet
R
Power Signals
Clock Signals
V_1.8
V_3.3
VSUS_3.3
VCCDA
VCCDACA1
VCCHA
VCCBA
VCCDACA2
VSSDA
VSSDACA
VSS
HCLK
SCLK
LTCLK
LOCLK
LRCLK
DCLKREF
HLCLK
Signal Name
Signal Name
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
I
CMOS
I
CMOS
O
CMOS
O
CMOS
I
CMOS
I
CMOS
I
CMOS
Type
Type
Core Power (1.8V)
I/O Buffer Power (3.3V)
System Memory Buffer Power (Separate 3.3V power plane for power down modes)
Display Power Signal (Connect to an isolated 1.8V plane with VCCDACA1 and
VCCDACA2)
Display Power Signal (Connect to an isolated 1.8V plane with VCCDA and
VCCDACA2)
Isolated 1.8V Power
Isolated 1.8V Power
Display Power Signal (Connect to an isolated 1.8V plane with VCCDA and
VCCDACA1)
Display Ground Signal
Display Ground Signal
Core Ground
Host Clock Input: Clock used on the host interface. Externally generated
66/100/133 MHz clock.
System Memory Clock: Clock used on the output buffers of system memory.
Externally generated 100 MHz clock.
Transmit Clock: LTCLK is an internally generated local memory clock used to
clock the input buffers of the SDRAM devices of the display cache.
Output Clock: LOCLK is an internally generated clock used to drive LRCLK.
Receive Clock: LRCLK is a display cache clock used to clock the input buffers of
the GMCH.
Display Interface Clock: DCLKREF is a 48 MHz clock generated by an external
clock synthesizer to the GMCH.
Hub Interface Clock: 66 MHz hub interface clock generated by an external clock
synthesizer.
Description
Description
Intel
®
82810E (GMCH)
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