NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 80

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
4.2.2.
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Table 10. Special Cycles
®
82810E (GMCH)
Special Cycles
A Special Cycle is defined when REQa[4:0] = 01000 and REQb[4:0]= xx001. The first address phase
Aa[35:3]# is undefined and can be driven to any value. The second address phase, Ab[15:8]# defines the
type of Special Cycle issued by the processor.
Table 10 specifies the cycle type and definition as well as the action taken by the GMCH when the
corresponding cycles are identified.
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
all others
BE[7:0}#
NOP
Shutdown
Flush
Halt
Sync
Flush Acknowledge
Stop Clock Acknowledge
SMI Acknowledge
Reserved
Special Cycle Type
This transaction has no side-effects.
This transaction is issued when an agent detects a severe
software error that prevents further processing. This cycle is
claimed by the GMCH. The GMCH issues a shutdown special
cycle on the hub interface. This cycle is retired on the processor
bus after it is terminated on the hub interface via a master abort
mechanism.
This transaction is issued when an agent has invalidated its
internal caches without writing back any modified lines. The
GMCH claims this cycle and retires it.
This transaction is issued when an agent executes a HLT
instruction and stops program execution. This cycle is claimed
by the GMCH and propagated to the hub interface as a Special
Halt Cycle. This cycle is retired on the processor bus after it is
terminated on the hub interface via a master abort mechanism.
This transaction is issued when an agent has written back all
modified lines and has invalidated its internal caches. The
GMCH claims this cycle and retires it.
This transaction is issued when an agent has completed a cache
sync and flush operation in response to an earlier FLUSH#
signal assertion. The GMCH claims this cycle and retires it.
This transaction is issued when an agent enters Stop Clock
mode. This cycle is claimed by the GMCH and propagated to the
hub interface as a Special Stop Grant Cycle. This cycle is
completed on the processor bus after it is terminated on the hub
interface via a master abort mechanism.
This transaction is first issued when an agent enters the System
Management Mode (SMM). Ab[7]# is also set at this entry point.
All subsequent transactions from the processor with Ab[7]# set
are treated by the GMCH as accesses to the SMM space. No
corresponding cycle is propagated to the hub interface. To exit
the System Management Mode the processor issues another
one of these cycles with the Ab[7]# bit deasserted. The SMM
space access is closed by the GMCH at this point.
Action Taken
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