CS1D-II102D Omron, CS1D-II102D Datasheet - Page 61

• Manufacturer Part Number: CS1D-II102D
• Description: CS1D Dual IO Interface Unit
• Manufacturer: Omron

Specifications of CS1D-II102D

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Specifications
Functions
26
Index Registers
Data Registers
Task Flags
Trace Memory
File Memory
Constant cycle time
Cycle time monitoring Possible (Unit stops operating if the cycle is too long):
I/O refreshing
Timing of special
refreshing for CPU
Bus Units
I/O memory holding
when changing oper-
ating modes
Load OFF
Function
Item
1 to 32,000 ms (Unit: 1 ms)
Note When Parallel Processing Mode is used in a Single
10 to 40,000 ms (Unit: 10 ms)
Note When Parallel Processing Mode is used in a Single
CPU Unit operation will stop if the peripheral servicing
cycle time exceeds 2 s (fixed).
Duplex CPU Systems: Cyclic refreshing, refreshing by
IORF (097).
Single CPU Systems: Cyclic refreshing, refreshing by IORF
(097), immediate refreshing
IORF(097) refreshes I/O bits allocated to Basic I/O Units
and Special I/O Units.
The CPU BUS UNIT I/O REFRESH (DLNK(226)) instruc-
tion can be used to execute cyclic refreshing of bits allo-
cated to CPU Bus Units.
Data links for Controller Link Units and SYSMAC LINK
Units, remote I/O for DeviceNet Units, and other special
refreshing for CPU Bus Units is performed at the I/O refresh
period and when the CPU BUS UNIT I/O REFRESH
(DLNK(226)) instruction is executed.
Depends on the ON/OFF status of the IOM Hold Bit in the
Auxiliary Area.
All outputs on Output Units can be turned OFF when the
CPU Unit is operating in RUN, MONITOR, or PROGRAM
mode.
CPU System, the cycle time for executing instruc-
tions is constant.
CPU System, the cycle time for executing instruc-
tions is monitored.
IR0 to IR15
Store PLC memory addresses for indirect addressing.
One register is 32 bits (2 words).
Index registers can be set to be shared by all tasks or to
be used independently by each task.
DR0 to DR15
Used to offset the PLC memory addresses in Index Reg-
isters when addressing words indirectly.
Data registers can be set to be shared by all tasks or to
be used independently by each task.
32 (TK0000 to TK0031)
Task Flags are read-only flags that are ON when the cor-
responding cyclic task is executable and OFF when the
corresponding task is not executable or in standby status.
4,000 words (trace data: 31 bits, 6 words)
Memory Cards: Compact flash memory cards can be
used (MS-DOS format).
EM file memory: The EM Area can be converted to file
memory (MS-DOS format).
Specifications
Specifications
Cycle time: 9-4 Computing the
Cycle Time
Constant cycle time: Programming
Manual (W394)
Cycle time: 9-4 Computing the
Cycle Time
Constant cycle time: Programming
Manual (W394)
I/O refreshing: 9-4 Computing the
Cycle Time
I/O refreshing method: Program-
ming Manual (W394)
9-1-3 I/O Refreshing and Peripheral
Servicing
I/O memory: SECTION 8 Memory
Areas
Holding memory areas when
changing operating modes: Pro-
gramming Manual (W394)
Holding I/O memory: 8-2-3 Data
Area Properties
Programming Manual (W394)
8-17 Index Registers
8-18 Data Registers
8-19 Task Flags
Programming Manual (W394)
Programming Manual (W394)
Reference
Reference
Section 2-1