CS4525-CNZR Cirrus Logic Inc, CS4525-CNZR Datasheet - Page 90

• Manufacturer Part Number: CS4525-CNZR
• Description: IC PWM Controller+power Stage
• Manufacturer: Cirrus Logic Inc
• Series: Popguard®r
• Type: Class Dr

Specifications of CS4525-CNZR

• Output Type: 2-Channel (Stereo) or 4-Channel (Quad)
• Max Output Power X Channels @ Load: 30W x 1 @ 4 Ohm; 15W x 2 @ 8 Ohm
• Voltage - Supply: 8 V ~ 18 V
• Features: ADC, Depop, I²C, I²S, Mute, PWM, Short-Circuit and Thermal Protection, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1586 - REFERENCE BOARD FOR CS4525 PWM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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9.20.1 SRC Lock State Transition Interrupt (SRCLock)
9.20.2 ADC Overflow Interrupt (ADCOvfl)
9.20.3 Channel Overflow Interrupt (ChOvfl)
Function:
This bit is read only. When set, indicates that the SRC has transitioned from an unlock to lock state or
from a lock state to an unlock state since the last read of this register. Conditions which cause the SRC
to transition states, such as loss of LRCK, SCLK, an LRCK ratio change, or the SRC achieving lock, will
cause this bit to be set. This interrupt bit is an edge-triggered event and will be cleared following a read
of this register.
If this bit is set, indicating a SRC state change condition, and the SRCLockM bit is set, the INT pin will go
active. To determine the current lock state of the SRC, read the SRCLockSt bit in the interrupt status reg-
ister.
Function:
This bit is read only. When set, indicates that an over-range condition occurred anywhere in the CS4525
ADC signal path and has been clipped to positive or negative full scale as appropriate since the last read
of this register. This interrupt bit is an edge-triggered event and will be cleared following a read of this
register.
If this bit is set, indicating an ADC over-range condition, and the ADCOvflM bit is set, the INT pin will go
active. To determine the current overflow state of the ADC, read the ADCOvflSt bit in the interrupt status
register.
Function:
This bit is read only. When set, indicates that the magnitude of an output sample on channel 1, 2, or the
Sub channel has exceeded full scale and has been clipped to positive or negative full scale as appropriate
since the last read of this register. This interrupt bit is an edge-triggered event and will be cleared following
a read of this register.
If this bit is set, indicating a channel over-range condition, and the ChOvflM bit is set, the INT pin will go
active. To determine the current overflow state of each channel, read the ChXOvflSt and SubOvflSt bits
in the interrupt status register.
SRCLock Setting
ADCOvfl Setting
ChOvfl Setting
0 .......................................... SRC lock state unchanged since last read of this register.
1 .......................................... SRC lock state changed since last read of this register.
0 .......................................... ADC overflow condition has not occurred since last read of this register.
1 .......................................... ADC overflow condition has occurred since last read of this register.
0 .......................................... A channel overflow condition has not occurred since last read of this register.
1 .......................................... A channel overflow condition has occurred since last read of this register.
SRC Lock State Change Status
ADC Overflow Event Status
Channel Overflow Event Status
CS4525
DS726PP3