CS4525-CNZR Cirrus Logic Inc, CS4525-CNZR Datasheet - Page 43

• Manufacturer Part Number: CS4525-CNZR
• Description: IC PWM Controller+power Stage
• Manufacturer: Cirrus Logic Inc
• Series: Popguard®r
• Type: Class Dr

Specifications of CS4525-CNZR

• Output Type: 2-Channel (Stereo) or 4-Channel (Quad)
• Max Output Power X Channels @ Load: 30W x 1 @ 4 Ohm; 15W x 2 @ 8 Ohm
• Voltage - Supply: 8 V ~ 18 V
• Features: ADC, Depop, I²C, I²S, Mute, PWM, Short-Circuit and Thermal Protection, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1586 - REFERENCE BOARD FOR CS4525 PWM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS726PP3
6.1.5
Auxiliary Serial Output
The CS4525 includes a stereo auxiliary serial output which allows an external device to leverage on its
internal signal processing and routing capabilities. The auxiliary serial output can receive its data from any
of the sources shown in the
The supported output data routing configurations are shown in
is configured to output channels A and B on the auxiliary output data left and right channels respectively.
The data output on each channel of AUX_SDOUT is set by the LChDSel[1:0] and RChDSel[1:0] bits in
the Aux Port Configuration register. The frequencies of AUX_LRCK and AUX_SCLK will vary based upon
the whether the serial input or analog input is being used and the frequency of the system clock for the
CS4525; the nominal values for these clocks are listed in
AUX_LRCK, and AUX_SDOUT are described in the
table on
The auxiliary port can be enabled using the EnAuxPort bit. When enabled, the port operates as a master
and clocks out data in the format dictated by the AuxI²S/LJ bit. When disabled, the AUX_LRCK,
AUX_SCLK, and AUX_SDOUT pins continuously drive a logic ‘0’. It should be noted that when the
CS4525 is configured for analog input, the AUX_LRCK, AUX_SCLK, and AUX_SDOUT pins will contin-
uously drive a logic ‘0’ if either the PDnADC bit or PDnAll bit is set.
Referenced Control
EnAuxPort ...........................
LChDSel[1:0].......................
RChDSel[1:0] ......................
AuxI²S/LJ.............................
PDnADC..............................
PDnAll .................................
Nominal Frequency of AUX_SCLK
Nominal Frequency of AUX_LRCK
LChDSel[1:0]
Applied System Clock from either
SYS_CLK or External Crystal
Frequency of LRCK Input
00
01
10
11
page
Signal
Output
Output
22.
Table 7. Nominal Switching Frequencies of the Auxiliary Serial Output
Aux Left Channel Data
Channel B X-Over LPF
Register Location
“Enable Aux Serial Port (EnAuxPort)” on page 72
“Aux Serial Port Left Channel Data Select (LChDSel[1:0])” on page 73
“Aux Serial Port Right Channel Data Select (RChDSel[1:0])” on page 72
“Aux/Delay Serial Port Digital Interface Format (AuxI²S/LJ)” on page 72
“Power Down ADC (PDnADC)” on page 88
“Power Down (PDnAll)” on page 89
Sub Channel
Channel A
Channel B
Digital Signal Flow
Table 6. Auxiliary Serial Port Data Output
32kHz, 44.1kHz,
Frequency of
Frequency of
18.432, 24.576, or 27.000MHz
SCLK Input
LRCK Input
or 48kHz
(Digital Input Mode)
ADC/SP = 0
diagram on
SCLK Input / 2
LRCK Input / 2
Frequency of
Frequency of
AUX Serial Audio I/O Port Switching Specifications
96kHz
RChDSel[1:0]
page
Table
00
01
10
11
Table 6
29.
7. The characteristics of AUX_SCLK,
18.432MHz
2.304MHz
48kHz
below. By default, the serial port
(Analog Input Mode)
Aux Right Channel Data
Channel B X-Over HPF
Not Applicable
ADC/SP = 1
24.576MHz
3.072MHz
Sub Channel
Channel A
Channel B
48kHz
CS4525
27.000MHz
52.734kHz
3.375MHz
43