CS4525-CNZR Cirrus Logic Inc, CS4525-CNZR Datasheet - Page 62

• Manufacturer Part Number: CS4525-CNZR
• Description: IC PWM Controller+power Stage
• Manufacturer: Cirrus Logic Inc
• Series: Popguard®r
• Type: Class Dr

Specifications of CS4525-CNZR

• Output Type: 2-Channel (Stereo) or 4-Channel (Quad)
• Max Output Power X Channels @ Load: 30W x 1 @ 4 Ohm; 15W x 2 @ 8 Ohm
• Voltage - Supply: 8 V ~ 18 V
• Features: ADC, Depop, I²C, I²S, Mute, PWM, Short-Circuit and Thermal Protection, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1586 - REFERENCE BOARD FOR CS4525 PWM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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6.6
6.6.1
6.6.2
Serial Audio Interfaces
The CS4525 interfaces to external digital audio devices via the serial audio input port and the auxiliary/delay
serial ports.
The serial audio input port provides support for I²S, Left-Justified and Right-Justified data formats and op-
erates in slave mode only, with LRCK and SCLK as inputs. The input LRCK signal must be equal to the
sample rate, Fs and must be synchronous to the serial bit clock, SCLK, which is used to sample the data
bits.
The auxiliary/delay serial port (available in software mode only) supports I²S and Left-Justified data formats
and operates in master mode only, with AUX_LRCK and AUX_SCLK as outputs.
Each of the supported formats is described in detail in sections
Audio Input Port Switching Specifications
page 21
For additional information, application note AN282 presents a tutorial of the 2-channel serial audio interface.
AN282 can be downloaded from the Cirrus Logic web site at http://www.cirrus.com.
I²S Data Format
In I²S format, data is received most significant bit first one SCLK delay after the transition of LRCK and is
valid on the rising edge of SCLK. The left channel data is presented when LRCK is low; the right channel
data is presented when LRCK is high.
Left-Justified Data Format
In Left-Justified format, data is received most significant bit first on the first SCLK after a LRCK transition
and is valid on the rising edge of SCLK. The left channel data is presented when LRCK is high and the
right channel data is presented when LRCK is low.
LRCK
SCLK
LRCK
SDIN
SDIN
SCLK
and
page 22
MSB
MSB
-1 -2 -3 -4 -5
-1 -2 -3 -4 -5
(respectively) for the precise timing and tolerances of each signal.
Figure 31. Left-Justified Serial Audio Formats
+5 +4
+5 +4
Left Channel
Left Channel
Figure 30. I²S Serial Audio Formats
+3 +2 +1
+3 +2 +1
LSB
LSB
and
AUX Serial Audio I/O Port Switching Specifications
6.6.1
MSB
MSB
-1 -2 -3 -4
-1 -2 -3 -4
-
6.6.3
below. Please refer to the
+5 +4
+5 +4
Right Channel
Right Channel
+3 +2 +1
+3 +2 +1
LSB
LSB
CS4525
DS726PP3
Serial
on