IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 71

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

December 2010 Altera Corporation
1
This chapter details the following timing diagrams for a RLDRAM II controller with
the following parameters:
■
■
■
Figure 9–1
Figure 9–1. Back-to-Back Writes
You can set the avl_size to 0x2 and hold avl_addr constant at 0x0 to perform the
same back-to-back write.
×36
Full rate
Burst length 2
shows back-to-back write to addresses 0 and 1.
Section IV. RLDRAM II Controller with UniPHY IP User Guide
External Memory Interface Handbook Volume 3
9. Timing Diagrams