IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 60

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–20
Figure 6–13. Word-Aligned Reads
Notes to
(1) For AFI, afi_rdata_en is required to be asserted one memory clock cycle before chip select (afi_cs_n) is asserted. In the half-rate afi_clk
(2) AFI requires that afi_rdata_en is driven for the duration of the read. In this example, it is driven to 11 for two half-rate afi_clks, which equates
(3) The afi_rdata_valid returns 15 (afi_rlat) controller clock (afi_clk) cycles after afi_rdata_en is asserted. Returned is when the
(4) Observe the alignment of returned read data relative to data on the bus.
External Memory Interface Handbook Volume 3
Section IV. RLDRAM II Controller with UniPHY IP User Guide
afi_rdata_valid
afi_rdata_en
domain, this requirement manifests as the controller driving 11 (as opposed to the 01) on afi_rdata_en.
to driving to 1, for the four memory clock cycles of this four-beat burst.
afi_rdata_valid signal is observed at the output of a register within the controller. A controller can use the afi_rlat value to determine when
to register to returned data, but this is unnecessary as the afi_rdata_valid is provided for the controller to use as an enable when registering
read data.
mem_cs_n
command
mem_dqs
afi_cas_n
afi_ras_n
mem_clk
afi_we_n
mem_dq
afi_rdata
afi_cs_n
Memory
Interface
afi_addr
afi_rlat
afi_dm
Figure
afi_clk
afi_ba
6–13:
00 00
11 11
00 00
01
ACT
0000000
11
11
00
Note 1
01
11
Note 2
Note 2
FFFFFFFF
FFFFFFFF
00 00
11
0
11
00
15
0020008
RD
11
00
Chapter 6: Functional Description—UniPHY
December 2010 Altera Corporation
11
PHY-to-Controller Interfaces
00
Note 3
11
Note 4
00