IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 19

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
HardCopy Migration Design Guidelines
HardCopy Migration Design Guidelines
December 2010 Altera Corporation
Simulate the System
f
f
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6. Click Generate to generate the system. Qsys generates the system and produces
7. In the Quartus II software, click Add/Remove Files in Project and add the .qip file
8. Compile your project in the Quartus II software.
During system generation, Qsys generates a functional simulation model—or
example design that includes a testbench—which you can use to simulate your
system in any Altera-supported simulation tool.
For information about the latest Altera-supported simulation tools, refer to the
Quartus II Software Release
For general information about simulating Altera IP cores, refer to
Designs
For information about simulating Qsys systems, refer to the
section in volume 1 of the Quartus II Handbook.
If you intend to target your design to a HardCopy
following design guidelines:
■
■
the <system name>.qip file that contains the assignments and information required
to process the IP core or system in the Quartus II Compiler.
to the project.
On the General Settings page of the DDR2 SDRAM Controller with UniPHY or
DDR3 SDRAM Controller with UniPHY MegaWizard, turn on HardCopy
Compatibility Mode, and then specify whether the Reconfigurable PLL Location
is Top_Bottom or Left_Right.
1
f
Enable run-time reconfiguration mode for all PLLs and DLLs instantiated in
interfaces that are configured in PLL and DLL slaves.
When turned on, the HardCopy Compatibility Mode option enables run-time
reconfiguration for all phase-locked loops (PLLs) and delay-locked loops (DLLs)
instantiated in memory interfaces that are configured in PLL and DLL masters,
and brings the necessary reconfiguration signals to the top level of the design.
in volume 3 of the Quartus II Handbook.
Altera recommends that you set the Reconfigurable PLL Location to the
same side as your memory interface.
“Top-Level HardCopy Migration Signals” on page 6–12
signals generated for HardCopy migration.
Notes.
Section IV. RLDRAM II Controller with UniPHY IP User Guide
®
device, ensure you use the
External Memory Interface Handbook Volume 3
System Design with Qsys
Simulating Altera
lists the top-level
2–9