IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 24

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

2–14
Table 2–5. Generated Directory Structure and Key Files—MegaWizard Plug-In Manager Simulation Flow (Verilog)
Table 2–6. Generated Directory Structure and Key Files—MegaWizard Plug-In Manager Simulation Flow (VHDL)
Table 2–7. Generated Directory Structure and Key Files—MegaWizard Plug-In Manager Example Design (Part 1 of 2)
External Memory Interface Handbook Volume 3
Section IV. RLDRAM II Controller with UniPHY IP User Guide
<working_dir>/<variation_name>
_sim/
<working_dir>/<variation_name>
_sim/
<working_dir>/<variation_name>
_sim/
<working_dir>/<variation_name>
_sim/
<working_dir>/<variation_name>
_sim/
<working_dir>/<variation_name>
_sim/
<working_dir>/<variation_name>
_sim/
<working_dir>/<variation_name>
_example_design_fileset/
<working_dir>/<variation_name>
_example_design_fileset/
<working_dir>/<variation_name>
_example_design_fileset
<working_dir>/<variation_name>
_example_design_fileset
<working_dir>/<variation_name>
_example_design_fileset/
Directory
Directory
Directory
Simulation
Table 2–5
simulation flow with the MegaWizard Plug-in Manager.
Table 2–6
simulation flow with the MegaWizard Plug-in Manager.
Example Design
Table 2–7
design with the MegaWizard Plug-in Manager
lists the generated directory structure and key files created by the Verilog
lists the generated directory structure and key files created by the VHDL
lists the generated directory structure and key files created for the example
<variation_name>.qip
<variation_name>.v
<variation_name>_*.v
<variation_name>_*.sv
<variation_name>.sdc
<variation_name>.v (for Verilog), or
<variation_name>.vho (for VHDL)
<variation_name>_*.v
<variation_name>_*.sv
<variation_name>_readme.txt
<variation_name>.vho
<variation_name>_*.vhd
<variation_name>_*.vho
vhdl_files.txt
File Name‘
File Name
File Name
UniPHY top-level wrapper.
UniPHY Verilog RTL files.
UniPHY SystemVerilog RTL files.
Readme text file.
QIP which refers to UniPHY RTL in
this fileset. This is distinct from
../<variation_name>.qip. This file is
included automatically in the
example project.
UniPHY top-level wrapper.
UniPHY Verilog RTL files.
UniPHY SystemVerilog RTL fies.
Synopsys constraints file.
UniPHY VHDL top-level module.
UniPHY simulation VHDL files.
File list text file.
December 2010 Altera Corporation
Description
Description
Description
Chapter 2: Getting Started
Generated Files