IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 63

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

December 2010 Altera Corporation
1
IP generation creates an example top-level project that shows you how to instantiate
and connect the controller.
The example top-level project contains a testbench, which is for use with Verilog HDL
only language simulators such as ModelSim-AE Verilog, and shows simple operation
of the memory interface.
For a VHDL-only simulation, use the VHDL IP functional simulation model.
The testbench contains the following blocks:
■
■
■
■
Figure 7–1
Figure 7–1. Testbench and Example Top-Level File
A synthesizable Avalon-MM example driver, which acts as a traffic generator
block and implements a pseudo-random pattern of reads and writes to a
parameterized number of addresses. The driver also monitors the data read from
the memory to ensure it matches the written data and asserts a failure otherwise.
An instance of the controller, which interfaces between the Avalon-MM interface
and the AFI.
The UniPHY IP, which serves as an interface between the memory controller and
external memory device(s) to perform read and write operations to the memory.
A memory model, which acts as a generic model that adheres to the memory
protocol specifications. Memory vendors also provide simulation models for
specific memory components that can be downloaded from their websites. This
block is available in Verilog HDL only.
shows the testbench and the example top-level file.
Testbench
Example Top-Level File
Example Driver
7. Functional Description—Example
Controller with
UniPHY
Section IV. RLDRAM II Controller with UniPHY IP User Guide
External Memory Interface Handbook Volume 3
Top-Level Project
Memory Model
Generated
Wizard-