IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 40

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–4
Table 5–2. Avalon-MM Slave Signals
External Memory Interface Handbook Volume 3
Section IV. RLDRAM II Controller with UniPHY IP User Guide
avl_size
avl_ready
avl_read_req
avl_write_req
avl_addr
avl_rdata_valid
avl_rdata
avl_wdata
Avalon-MM Slave Interface
Signal
1
Table 5–2
The data width of the Avalon-MM interface is restricted to powers of two when using
SOPC Builder or Qsys. Non-power-of-two data widths are supported when using the
MegaWizard Plug-In Manager.
18, 36, 72, 144
18, 36, 72, 144
shows the list of signals of the controller’s Avalon-MM slave interface.
1 to 11
Width
≤
1
1
1
25
1
Direction
Out
Out
Out
In
In
In
In
In
burstcount
waitrequest_n
read
write
address
readdatavalid
readdata
writedata
Avalon-MM Signal Type
Chapter 5: Functional Description—Controller
December 2010 Altera Corporation
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Description
Signal Description