IPR-RLDII/UNI Altera, IPR-RLDII/UNI Datasheet - Page 54

• Manufacturer Part Number: IPR-RLDII/UNI
• Description: IP CORE Renewal Of IP-RLDII/UNI
• Manufacturer: Altera

Specifications of IPR-RLDII/UNI

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GZ, Stratix III, Stratix IV, HardCopy III
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–14
Table 6–9. Parameters (Part 1 of 2)
External Memory Interface Handbook Volume 3
Section IV. RLDRAM II Controller with UniPHY IP User Guide
Parameter Name
AFI_RATIO
MEM_IF_DQS_WIDTH
MEM_ADDRESS_WIDTH
MEM_BANK_WIDTH
MEM_CHIP_SELECT_WIDTH
MEM_CONTROL_WIDTH
MEM_DM_WIDTH
MEM_DQ_WIDTH
MEM_READ_DQS_WIDTH
MEM_WRITE_DQS_WIDTH
OCT_SERIES_TERM_CONTROL
_WIDTH
OCT_PARALLEL_TERM_
CONTROL_WIDTH
AFI_ADDRESS_WIDTH
AFI_BANK_WIDTH
AFI_CHIP_SELECT_WIDTH
AFI_DATA_MASK_WIDTH
AFI_CONTROL_WIDTH
AFI_DATA_WIDTH
AFI_DQS_WIDTH
DLL_DELAY_CTRL_WIDTH
NUM_SUBGROUP_PER_READ_DQS
QVLD_EXTRA_FLOP_STAGES
READ_VALID_TIMEOUT_WIDTH
READ_VALID_FIFO_WRITE_ADDR
_WIDTH
READ_VALID_FIFO_READ_
ADDR_WIDTH
MAX_LATENCY_COUNT_WIDTH
MAX_READ_LATENCY
READ_FIFO_READ_ADDR_WIDTH
READ_FIFO_WRITE_ADDR_WIDTH —
MAX_WRITE_LATENCY_
COUNT_WIDTH
INIT_COUNT_WIDTH
MRSC_COUNT_WIDTH
INIT_NOP_COUNT_WIDTH
Table 6–9
shows the parameters that
Description
AFI_RATIO is 1 in full-rate designs.
AFI_RATIO is 2 for half-rate designs.
The number of DQS pins in the interface.
The address width of the specified memory device.
The bank width of the specified memory device.
The chip select width of the specified memory device.
The control width of the specified memory device.
The DM width of the specified memory device.
The DQ width of the specified memory device.
The READ DQS width of the specified memory device.
The WRITE DQS width of the specified memory device.
—
—
The AFI address width, derived from the corresponding memory interface width.
The AFI bank width, derived from the corresponding memory interface width.
The AFI chip-select width, derived from the corresponding memory interface width.
The AFI data mask width.
The AFI control width, derived from the corresponding memory interface width.
The AFI data width.
The AFI DQS width.
The DLL delay output control width.
A read datapath parameter for timing purposes.
A read datapath parameter for timing purposes.
A read datapath parameter; calibration fails when the timeout counter expires.
A read datapath parameter; the write address width for half-rate clocks.
A read datapath parameter; the read address width for full-rate clocks.
A latency calibration parameter; the maximum latency count width.
A latency calibration parameter; the maximum read latency.
—
A write datapath parameter; the maximum write latency count width.
An initailization sequence.
An RLDRAM II-specific initialization parameter.
An RLDRAM II-specific initialization parameter.
Table 6–5
through
Chapter 6: Functional Description—UniPHY
Table 6–7
December 2010 Altera Corporation
mention.
UniPHY Signals